Lines Matching full:capability

74 stored internally as ten 32\-bit capability vectors and for simplicity
79 Upon toolkit initialization, the capability vectors are populated through
81 environment variable capability bit modifications are applied. After toolkit
89 .SS "Notable Capability Bits for LV0"
90 .IX Subsection "Notable Capability Bits for LV0"
91 The following are notable capability bits from logical vector 0 (LV0)
132 .SS "Notable Capability Bits for LV1"
133 .IX Subsection "Notable Capability Bits for LV1"
134 The following are notable capability bits from logical vector 1 (LV1)
165 .SS "Notable Capability Bits for LV2"
166 .IX Subsection "Notable Capability Bits for LV2"
167 The following are notable capability bits from logical vector 2 (LV2)
184 .SS "Notable Capability Bits for LV3"
185 .IX Subsection "Notable Capability Bits for LV3"
186 The following are notable capability bits from logical vector 3 (LV3)
195 .SS "Notable Capability Bits for LV4"
196 .IX Subsection "Notable Capability Bits for LV4"
197 The following are notable capability bits from logical vector 4 (LV4)
213 the default capability vector values at library initialization time.
221 capability vector pair with the provided value. To keep compatibility with the
223 <env OPENSSL_ia32cap=LV0:LV1>, the next capability vector pairs will be set to zero.
225 To illustrate, the following will zero all capability bits in logical vectors 1 and further
230 The following will zero all capability bits in logical vectors 2 and further:
234 The following will zero all capability bits only in logical vector 1:
252 Not all capability bits are copied from CPUID output verbatim. An example