Lines Matching full:bit

74 stored internally as ten 32\-bit capability vectors and for simplicity
75 represented logically below as five 64\-bit vectors. This logical
81 environment variable capability bit modifications are applied. After toolkit
94 .IP "bit #0+4 denoting presence of Time-Stamp Counter;" 4
95 .IX Item "bit #0+4 denoting presence of Time-Stamp Counter;"
97 .IP "bit #0+19 denoting availability of CLFLUSH instruction;" 4
98 .IX Item "bit #0+19 denoting availability of CLFLUSH instruction;"
99 .IP "bit #0+20, reserved by Intel, is used to choose among RC4 code paths;" 4
100 .IX Item "bit #0+20, reserved by Intel, is used to choose among RC4 code paths;"
101 .IP "bit #0+23 denoting MMX support;" 4
102 .IX Item "bit #0+23 denoting MMX support;"
103 .IP "bit #0+24, FXSR bit, denoting availability of XMM registers;" 4
104 .IX Item "bit #0+24, FXSR bit, denoting availability of XMM registers;"
105 .IP "bit #0+25 denoting SSE support;" 4
106 .IX Item "bit #0+25 denoting SSE support;"
107 .IP "bit #0+26 denoting SSE2 support;" 4
108 .IX Item "bit #0+26 denoting SSE2 support;"
109 .IP "bit #0+28 denoting Hyperthreading, which is used to distinguish cores with shared cache;" 4
110 .IX Item "bit #0+28 denoting Hyperthreading, which is used to distinguish cores with shared cache;"
111 .IP "bit #0+30, reserved by Intel, denotes specifically Intel CPUs;" 4
112 .IX Item "bit #0+30, reserved by Intel, denotes specifically Intel CPUs;"
113 .IP "bit #0+33 denoting availability of PCLMULQDQ instruction;" 4
114 .IX Item "bit #0+33 denoting availability of PCLMULQDQ instruction;"
115 .IP "bit #0+41 denoting SSSE3, Supplemental SSE3, support;" 4
116 .IX Item "bit #0+41 denoting SSSE3, Supplemental SSE3, support;"
117 .IP "bit #0+43 denoting AMD XOP support (forced to zero on non-AMD CPUs);" 4
118 .IX Item "bit #0+43 denoting AMD XOP support (forced to zero on non-AMD CPUs);"
119 .IP "bit #0+54 denoting availability of MOVBE instruction;" 4
120 .IX Item "bit #0+54 denoting availability of MOVBE instruction;"
121 .IP "bit #0+57 denoting AES-NI instruction set extension;" 4
122 .IX Item "bit #0+57 denoting AES-NI instruction set extension;"
123 .IP "bit #0+58, XSAVE bit, lack of which in combination with MOVBE is used to identify Atom Silverm…
124 .IX Item "bit #0+58, XSAVE bit, lack of which in combination with MOVBE is used to identify Atom Si…
125 .IP "bit #0+59, OSXSAVE bit, denoting availability of YMM registers;" 4
126 .IX Item "bit #0+59, OSXSAVE bit, denoting availability of YMM registers;"
127 .IP "bit #0+60 denoting AVX extension;" 4
128 .IX Item "bit #0+60 denoting AVX extension;"
129 .IP "bit #0+62 denoting availability of RDRAND instruction;" 4
130 .IX Item "bit #0+62 denoting availability of RDRAND instruction;"
137 .IP "bit #64+3 denoting availability of BMI1 instructions, e.g. ANDN;" 4
138 .IX Item "bit #64+3 denoting availability of BMI1 instructions, e.g. ANDN;"
140 .IP "bit #64+5 denoting availability of AVX2 instructions;" 4
141 .IX Item "bit #64+5 denoting availability of AVX2 instructions;"
142 .IP "bit #64+8 denoting availability of BMI2 instructions, e.g. MULX and RORX;" 4
143 .IX Item "bit #64+8 denoting availability of BMI2 instructions, e.g. MULX and RORX;"
144 .IP "bit #64+16 denoting availability of AVX512F extension;" 4
145 .IX Item "bit #64+16 denoting availability of AVX512F extension;"
146 .IP "bit #64+17 denoting availability of AVX512DQ extension;" 4
147 .IX Item "bit #64+17 denoting availability of AVX512DQ extension;"
148 .IP "bit #64+18 denoting availability of RDSEED instruction;" 4
149 .IX Item "bit #64+18 denoting availability of RDSEED instruction;"
150 .IP "bit #64+19 denoting availability of ADCX and ADOX instructions;" 4
151 .IX Item "bit #64+19 denoting availability of ADCX and ADOX instructions;"
152 .IP "bit #64+21 denoting availability of AVX512IFMA extension;" 4
153 .IX Item "bit #64+21 denoting availability of AVX512IFMA extension;"
154 .IP "bit #64+29 denoting availability of SHA extension;" 4
155 .IX Item "bit #64+29 denoting availability of SHA extension;"
156 .IP "bit #64+30 denoting availability of AVX512BW extension;" 4
157 .IX Item "bit #64+30 denoting availability of AVX512BW extension;"
158 .IP "bit #64+31 denoting availability of AVX512VL extension;" 4
159 .IX Item "bit #64+31 denoting availability of AVX512VL extension;"
160 .IP "bit #64+41 denoting availability of VAES extension;" 4
161 .IX Item "bit #64+41 denoting availability of VAES extension;"
162 .IP "bit #64+42 denoting availability of VPCLMULQDQ extension;" 4
163 .IX Item "bit #64+42 denoting availability of VPCLMULQDQ extension;"
170 .IP "bit #128+15 denoting availability of Hybrid CPU;" 4
171 .IX Item "bit #128+15 denoting availability of Hybrid CPU;"
173 .IP "bit #128+29 denoting support for IA32_ARCH_CAPABILITIES MSR;" 4
174 .IX Item "bit #128+29 denoting support for IA32_ARCH_CAPABILITIES MSR;"
175 .IP "bit #128+32 denoting availability of SHA512 extension;" 4
176 .IX Item "bit #128+32 denoting availability of SHA512 extension;"
177 .IP "bit #128+33 denoting availability of SM3 extension;" 4
178 .IX Item "bit #128+33 denoting availability of SM3 extension;"
179 .IP "bit #128+34 denoting availability of SM4 extension;" 4
180 .IX Item "bit #128+34 denoting availability of SM4 extension;"
181 .IP "bit #128+55 denoting availability of AVX-IFMA extension;" 4
182 .IX Item "bit #128+55 denoting availability of AVX-IFMA extension;"
189 .IP "bit #192+19 denoting availability of AVX10 Converged Vector ISA extension;" 4
190 .IX Item "bit #192+19 denoting availability of AVX10 Converged Vector ISA extension;"
192 .IP "bit #192+21 denoting availability of APX_F extension;" 4
193 .IX Item "bit #192+21 denoting availability of APX_F extension;"
203 .IP "bit #256+48 denoting AVX10 XMM support;" 4
204 .IX Item "bit #256+48 denoting AVX10 XMM support;"
205 .IP "bit #256+49 denoting AVX10 YMM support;" 4
206 .IX Item "bit #256+49 denoting AVX10 YMM support;"
207 .IP "bit #256+50 denoting AVX10 ZMM support;" 4
208 .IX Item "bit #256+50 denoting AVX10 ZMM support;"
214 The variable consists of a series of 64\-bit numbers representing each
238 The '\fB~\fR' character is used to specify a bit mask of the extensions to be disabled for
245 The following will disable AESNI (LV0 bit 57) and VAES (LV1 bit 41)
253 of this is the somewhat less intuitive clearing of LV0 bit #28, or ~0x10000000