Lines Matching +full:64 +full:m

29 .    if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch
30 .    if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\"  diablo 12 pitch
75 .    ds #V .8m
76 .    ds #F .3m
81 .    ds #H ((1u-(\\\\n(.fu%2u))*.13m)
82 .    ds #V .6m
101 .    ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u'
219 .IP "bit #64+3 denoting availability of \s-1BMI1\s0 instructions, e.g. \s-1ANDN\s0;" 4
220 .IX Item "bit #64+3 denoting availability of BMI1 instructions, e.g. ANDN;"
222 .IP "bit #64+5 denoting availability of \s-1AVX2\s0 instructions;" 4
223 .IX Item "bit #64+5 denoting availability of AVX2 instructions;"
224 .IP "bit #64+8 denoting availability of \s-1BMI2\s0 instructions, e.g. \s-1MULX\s0 and \s-1RORX\s0;…
225 .IX Item "bit #64+8 denoting availability of BMI2 instructions, e.g. MULX and RORX;"
226 .IP "bit #64+16 denoting availability of \s-1AVX512F\s0 extension;" 4
227 .IX Item "bit #64+16 denoting availability of AVX512F extension;"
228 .IP "bit #64+17 denoting availability of \s-1AVX512DQ\s0 extension;" 4
229 .IX Item "bit #64+17 denoting availability of AVX512DQ extension;"
230 .IP "bit #64+18 denoting availability of \s-1RDSEED\s0 instruction;" 4
231 .IX Item "bit #64+18 denoting availability of RDSEED instruction;"
232 .IP "bit #64+19 denoting availability of \s-1ADCX\s0 and \s-1ADOX\s0 instructions;" 4
233 .IX Item "bit #64+19 denoting availability of ADCX and ADOX instructions;"
234 .IP "bit #64+21 denoting availability of VPMADD52[\s-1LH\s0]UQ instructions, aka \s-1AVX512IFMA\s0 …
235 .IX Item "bit #64+21 denoting availability of VPMADD52[LH]UQ instructions, aka AVX512IFMA extension…
236 .IP "bit #64+29 denoting availability of \s-1SHA\s0 extension;" 4
237 .IX Item "bit #64+29 denoting availability of SHA extension;"
238 .IP "bit #64+30 denoting availability of \s-1AVX512BW\s0 extension;" 4
239 .IX Item "bit #64+30 denoting availability of AVX512BW extension;"
240 .IP "bit #64+31 denoting availability of \s-1AVX512VL\s0 extension;" 4
241 .IX Item "bit #64+31 denoting availability of AVX512VL extension;"
242 .IP "bit #64+41 denoting availability of \s-1VAES\s0 extension;" 4
243 .IX Item "bit #64+41 denoting availability of VAES extension;"
244 .IP "bit #64+42 denoting availability of \s-1VPCLMULQDQ\s0 extension;" 4
245 .IX Item "bit #64+42 denoting availability of VPCLMULQDQ extension;"