Lines Matching +full:10 +full:g +full:- +full:support
18 .\" Set up some character translations and predefined strings. \*(-- will
24 .tr \(*W-
27 . ds -- \(*W-
29 . if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch
30 . if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch
37 . ds -- \|\(em\|
71 .\" Fear. Run. Save yourself. No user-serviceable parts.
81 . ds #H ((1u-(\\\\n(.fu%2u))*.13m)
97 . ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u"
98 . ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u'
99 . ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u'
100 . ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u'
101 . ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u'
102 . ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u'
104 . \" troff and (daisy-wheel) nroff accents
123 . ds d- d\h'-1'\(ga
124 . ds D- D\h'-1'\(hy
134 .TH OPENSSL_IA32CAP 3ossl "2023-09-19" "3.0.11" "OpenSSL"
140 OPENSSL_ia32cap \- the x86[_64] processor capabilities vector
150 by processor in \s-1EDX:ECX\s0 register pair after executing \s-1CPUID\s0 instruction
156 .IP "bit #4 denoting presence of Time-Stamp Counter." 4
157 .IX Item "bit #4 denoting presence of Time-Stamp Counter."
159 .IP "bit #19 denoting availability of \s-1CLFLUSH\s0 instruction;" 4
161 .IP "bit #20, reserved by Intel, is used to choose among \s-1RC4\s0 code paths;" 4
163 .IP "bit #23 denoting \s-1MMX\s0 support;" 4
164 .IX Item "bit #23 denoting MMX support;"
165 .IP "bit #24, \s-1FXSR\s0 bit, denoting availability of \s-1XMM\s0 registers;" 4
167 .IP "bit #25 denoting \s-1SSE\s0 support;" 4
168 .IX Item "bit #25 denoting SSE support;"
169 .IP "bit #26 denoting \s-1SSE2\s0 support;" 4
170 .IX Item "bit #26 denoting SSE2 support;"
175 .IP "bit #33 denoting availability of \s-1PCLMULQDQ\s0 instruction;" 4
177 .IP "bit #41 denoting \s-1SSSE3,\s0 Supplemental \s-1SSE3,\s0 support;" 4
178 .IX Item "bit #41 denoting SSSE3, Supplemental SSE3, support;"
179 .IP "bit #43 denoting \s-1AMD XOP\s0 support (forced to zero on non-AMD CPUs);" 4
180 .IX Item "bit #43 denoting AMD XOP support (forced to zero on non-AMD CPUs);"
181 .IP "bit #54 denoting availability of \s-1MOVBE\s0 instruction;" 4
183 .IP "bit #57 denoting AES-NI instruction set extension;" 4
184 .IX Item "bit #57 denoting AES-NI instruction set extension;"
185 .IP "bit #58, \s-1XSAVE\s0 bit, lack of which in combination with \s-1MOVBE\s0 is used to identify …
187 .IP "bit #59, \s-1OSXSAVE\s0 bit, denoting availability of \s-1YMM\s0 registers;" 4
189 .IP "bit #60 denoting \s-1AVX\s0 extension;" 4
191 .IP "bit #62 denoting availability of \s-1RDRAND\s0 instruction;" 4
195 For example, in 32\-bit application context clearing bit #26 at run-time
196 disables high-performance \s-1SSE2\s0 code present in the crypto library, while
197 clearing bit #24 disables \s-1SSE2\s0 code operating on 128\-bit \s-1XMM\s0 register
199 executed on \s-1SSE2\s0 capable \s-1CPU,\s0 but under control of \s-1OS\s0 that does not
200 enable \s-1XMM\s0 registers. Historically address of the capability vector copy
207 effect. Alternatively you can reconfigure the toolkit with no\-sse2
211 variable\*(R" terms. The truth is that it's not copied from \s-1CPUID\s0 output
214 on whether or not expensive countermeasures against cache-timing attacks
215 are applied, most notably in \s-1AES\s0 assembler module.
217 The capability vector is further extended with \s-1EBX\s0 value returned by
218 \&\s-1CPUID\s0 with EAX=7 and ECX=0 as input. Following bits are significant:
219 .IP "bit #64+3 denoting availability of \s-1BMI1\s0 instructions, e.g. \s-1ANDN\s0;" 4
220 .IX Item "bit #64+3 denoting availability of BMI1 instructions, e.g. ANDN;"
222 .IP "bit #64+5 denoting availability of \s-1AVX2\s0 instructions;" 4
224 .IP "bit #64+8 denoting availability of \s-1BMI2\s0 instructions, e.g. \s-1MULX\s0 and \s-1RORX\s0;…
225 .IX Item "bit #64+8 denoting availability of BMI2 instructions, e.g. MULX and RORX;"
226 .IP "bit #64+16 denoting availability of \s-1AVX512F\s0 extension;" 4
228 .IP "bit #64+17 denoting availability of \s-1AVX512DQ\s0 extension;" 4
230 .IP "bit #64+18 denoting availability of \s-1RDSEED\s0 instruction;" 4
232 .IP "bit #64+19 denoting availability of \s-1ADCX\s0 and \s-1ADOX\s0 instructions;" 4
234 .IP "bit #64+21 denoting availability of VPMADD52[\s-1LH\s0]UQ instructions, aka \s-1AVX512IFMA\s0 …
236 .IP "bit #64+29 denoting availability of \s-1SHA\s0 extension;" 4
238 .IP "bit #64+30 denoting availability of \s-1AVX512BW\s0 extension;" 4
240 .IP "bit #64+31 denoting availability of \s-1AVX512VL\s0 extension;" 4
242 .IP "bit #64+41 denoting availability of \s-1VAES\s0 extension;" 4
244 .IP "bit #64+42 denoting availability of \s-1VPCLMULQDQ\s0 extension;" 4
250 \&\f(CW\*(C`:~0x20\*(C'\fR would disable \s-1AVX2\s0 code paths, and \f(CW\*(C`:0\*(C'\fR \- all po…
257 Copyright 2004\-2021 The OpenSSL Project Authors. All Rights Reserved.
261 in the file \s-1LICENSE\s0 in the source distribution or at