Lines Matching refs:__bits
106 __asm __volatile("mfspr %0, 512" : "=r" ((__env)->__bits.__reg))
108 __asm __volatile("mtspr 512,%0;isync" :: "r" ((__env).__bits.__reg))
130 } __bits; member
141 __r.__bits.__reg &= ~__excepts; in feclearexcept()
152 *__flagp = __r.__bits.__reg & __excepts; in fegetexceptflag()
164 __r.__bits.__reg &= ~__excepts; in fesetexceptflag()
165 __r.__bits.__reg |= *__flagp & __excepts; in fesetexceptflag()
181 __r.__bits.__reg |= __excepts; in feraiseexcept()
193 return (__r.__bits.__reg & __excepts); in fetestexcept()
202 return (__r.__bits.__reg & _ROUND_MASK); in fegetround()
213 __r.__bits.__reg &= ~_ROUND_MASK; in fesetround()
214 __r.__bits.__reg |= __round; in fesetround()
225 *__envp = __r.__bits.__reg; in fegetenv()
235 *__envp = __r.__bits.__reg; in feholdexcept()
236 __r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK); in feholdexcept()
246 __r.__bits.__reg = *__envp; in fesetenv()
257 __r.__bits.__reg &= FE_ALL_EXCEPT; in feupdateenv()
258 __r.__bits.__reg |= *__envp; in feupdateenv()
272 __oldmask = __r.__bits.__reg; in feenableexcept()
273 __r.__bits.__reg |= (__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT; in feenableexcept()
285 __oldmask = __r.__bits.__reg; in fedisableexcept()
286 __r.__bits.__reg &= ~((__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT); in fedisableexcept()
298 return ((__r.__bits.__reg & _ENABLE_MASK) << _FPUSW_SHIFT); in fegetexcept()