Lines Matching refs:ProcModel
105 unsigned EmitRegisterFileTables(const CodeGenProcModel &ProcModel,
107 void EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,
109 void EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel,
113 void EmitProcessorResourceSubUnits(const CodeGenProcModel &ProcModel,
115 void EmitProcessorResources(const CodeGenProcModel &ProcModel,
118 const CodeGenProcModel &ProcModel);
120 const CodeGenProcModel &ProcModel);
123 const CodeGenProcModel &ProcModel);
124 void GenSchedClassTables(const CodeGenProcModel &ProcModel,
444 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) { in EmitStageAndOperandCycleData() local
446 if (!ItinsDefSet.insert(ProcModel.ItinsDef).second) in EmitStageAndOperandCycleData()
449 RecVec FUs = ProcModel.ItinsDef->getValueAsListOfDefs("FU"); in EmitStageAndOperandCycleData()
453 StringRef Name = ProcModel.ItinsDef->getName(); in EmitStageAndOperandCycleData()
463 RecVec BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP"); in EmitStageAndOperandCycleData()
498 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) { in EmitStageAndOperandCycleData() local
504 if (!ProcModel.hasItineraries()) in EmitStageAndOperandCycleData()
507 StringRef Name = ProcModel.ItinsDef->getName(); in EmitStageAndOperandCycleData()
510 assert(ProcModel.ItinDefList.size() == ItinList.size() && "bad Itins"); in EmitStageAndOperandCycleData()
516 Record *ItinData = ProcModel.ItinDefList[SchedClassIdx]; in EmitStageAndOperandCycleData()
678 const CodeGenProcModel &ProcModel, raw_ostream &OS) { in EmitProcessorResourceSubUnits() argument
679 OS << "\nstatic const unsigned " << ProcModel.ModelName in EmitProcessorResourceSubUnits()
683 for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) { in EmitProcessorResourceSubUnits()
684 Record *PRDef = ProcModel.ProcResourceDefs[i]; in EmitProcessorResourceSubUnits()
690 SchedModels.findProcResUnits(RUDef, ProcModel, PRDef->getLoc()); in EmitProcessorResourceSubUnits()
692 OS << " " << ProcModel.getProcResourceIdx(RU) << ", "; in EmitProcessorResourceSubUnits()
700 static void EmitRetireControlUnitInfo(const CodeGenProcModel &ProcModel, in EmitRetireControlUnitInfo() argument
703 if (Record *RCU = ProcModel.RetireControlUnit) { in EmitRetireControlUnitInfo()
714 static void EmitRegisterFileInfo(const CodeGenProcModel &ProcModel, in EmitRegisterFileInfo() argument
718 OS << ProcModel.ModelName << "RegisterFiles,\n " << (1 + NumRegisterFiles); in EmitRegisterFileInfo()
724 OS << ProcModel.ModelName << "RegisterCosts,\n "; in EmitRegisterFileInfo()
731 SubtargetEmitter::EmitRegisterFileTables(const CodeGenProcModel &ProcModel, in EmitRegisterFileTables() argument
733 if (llvm::all_of(ProcModel.RegisterFiles, [](const CodeGenRegisterFile &RF) { in EmitRegisterFileTables()
740 OS << "static const llvm::MCRegisterCostEntry " << ProcModel.ModelName in EmitRegisterFileTables()
744 for (const CodeGenRegisterFile &RF : ProcModel.RegisterFiles) { in EmitRegisterFileTables()
763 OS << "static const llvm::MCRegisterFileDesc " << ProcModel.ModelName in EmitRegisterFileTables()
769 for (const CodeGenRegisterFile &RD : ProcModel.RegisterFiles) { in EmitRegisterFileTables()
783 void SubtargetEmitter::EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel, in EmitLoadStoreQueueInfo() argument
786 if (ProcModel.LoadQueue) { in EmitLoadStoreQueueInfo()
787 const Record *Queue = ProcModel.LoadQueue->getValueAsDef("QueueDescriptor"); in EmitLoadStoreQueueInfo()
788 QueueID = 1 + std::distance(ProcModel.ProcResourceDefs.begin(), in EmitLoadStoreQueueInfo()
789 find(ProcModel.ProcResourceDefs, Queue)); in EmitLoadStoreQueueInfo()
794 if (ProcModel.StoreQueue) { in EmitLoadStoreQueueInfo()
796 ProcModel.StoreQueue->getValueAsDef("QueueDescriptor"); in EmitLoadStoreQueueInfo()
797 QueueID = 1 + std::distance(ProcModel.ProcResourceDefs.begin(), in EmitLoadStoreQueueInfo()
798 find(ProcModel.ProcResourceDefs, Queue)); in EmitLoadStoreQueueInfo()
803 void SubtargetEmitter::EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel, in EmitExtraProcessorInfo() argument
807 unsigned NumCostEntries = EmitRegisterFileTables(ProcModel, OS); in EmitExtraProcessorInfo()
810 OS << "\nstatic const llvm::MCExtraProcessorInfo " << ProcModel.ModelName in EmitExtraProcessorInfo()
814 EmitRetireControlUnitInfo(ProcModel, OS); in EmitExtraProcessorInfo()
818 EmitRegisterFileInfo(ProcModel, ProcModel.RegisterFiles.size(), in EmitExtraProcessorInfo()
822 EmitLoadStoreQueueInfo(ProcModel, OS); in EmitExtraProcessorInfo()
827 void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel, in EmitProcessorResources() argument
829 EmitProcessorResourceSubUnits(ProcModel, OS); in EmitProcessorResources()
832 OS << "static const llvm::MCProcResourceDesc " << ProcModel.ModelName in EmitProcessorResources()
838 for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) { in EmitProcessorResources()
839 Record *PRDef = ProcModel.ProcResourceDefs[i]; in EmitProcessorResources()
856 ProcModel, PRDef->getLoc()); in EmitProcessorResources()
857 SuperIdx = ProcModel.getProcResourceIdx(SuperDef); in EmitProcessorResources()
867 OS << ProcModel.ModelName << "ProcResourceSubUnits + " in EmitProcessorResources()
884 const CodeGenProcModel &ProcModel) { in FindWriteResources() argument
897 if (&SchedModels.getProcModel(ModelDef) != &ProcModel) in FindWriteResources()
904 ProcModel.ModelName + in FindWriteResources()
913 for (Record *WR : ProcModel.WriteResDefs) { in FindWriteResources()
921 ProcModel.ModelName); in FindWriteResources()
934 PrintFatalError(ProcModel.ModelDef->getLoc(), in FindWriteResources()
944 const CodeGenProcModel &ProcModel) { in FindReadAdvance() argument
956 if (&SchedModels.getProcModel(ModelDef) != &ProcModel) in FindReadAdvance()
963 ProcModel.ModelName + in FindReadAdvance()
972 for (Record *RA : ProcModel.ReadAdvanceDefs) { in FindReadAdvance()
980 ProcModel.ModelName); in FindReadAdvance()
993 PrintFatalError(ProcModel.ModelDef->getLoc(), in FindReadAdvance()
1050 void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel, in GenSchedClassTables() argument
1054 if (!ProcModel.hasInstrSchedModel()) in GenSchedClassTables()
1075 if (CGT.ProcIndex == ProcModel.Index) { in GenSchedClassTables()
1090 if (!is_contained(SC.ProcIndices, ProcModel.Index)) in GenSchedClassTables()
1101 if (&ProcModel == &SchedModels.getProcModel(RWModelDef)) { in GenSchedClassTables()
1115 for (Record *I : ProcModel.ItinRWDefs) { in GenSchedClassTables()
1124 LLVM_DEBUG(dbgs() << ProcModel.ModelName in GenSchedClassTables()
1137 SchedModels.expandRWSeqForProc(W, WriteSeq, /*IsRead=*/false, ProcModel); in GenSchedClassTables()
1146 if (!ProcModel.hasReadOfWrite(SchedModels.getSchedWrite(WriteID).TheDef)) in GenSchedClassTables()
1153 FindWriteResources(SchedModels.getSchedWrite(WS), ProcModel); in GenSchedClassTables()
1215 ExpandProcResources(PRVec, ReleaseAtCycles, AcquireAtCycles, ProcModel); in GenSchedClassTables()
1221 WPREntry.ProcResourceIdx = ProcModel.getProcResourceIdx(PRVec[PRIdx]); in GenSchedClassTables()
1269 FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel); in GenSchedClassTables()
1541 for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) { in EmitSchedModel() local
1542 GenSchedClassTables(ProcModel, SchedTables); in EmitSchedModel()