Lines Matching refs:ModelDef
896 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel"); in FindWriteResources() local
897 if (&SchedModels.getProcModel(ModelDef) != &ProcModel) in FindWriteResources()
934 PrintFatalError(ProcModel.ModelDef->getLoc(), in FindWriteResources()
955 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel"); in FindReadAdvance() local
956 if (&SchedModels.getProcModel(ModelDef) != &ProcModel) in FindReadAdvance()
993 PrintFatalError(ProcModel.ModelDef->getLoc(), in FindReadAdvance()
1461 PrintFatalError(PM.ModelDef->getLoc(), in EmitProcessorModels()
1468 EmitProcessorProp(OS, PM.ModelDef, "IssueWidth", ','); in EmitProcessorModels()
1469 EmitProcessorProp(OS, PM.ModelDef, "MicroOpBufferSize", ','); in EmitProcessorModels()
1470 EmitProcessorProp(OS, PM.ModelDef, "LoopMicroOpBufferSize", ','); in EmitProcessorModels()
1471 EmitProcessorProp(OS, PM.ModelDef, "LoadLatency", ','); in EmitProcessorModels()
1472 EmitProcessorProp(OS, PM.ModelDef, "HighLatency", ','); in EmitProcessorModels()
1473 EmitProcessorProp(OS, PM.ModelDef, "MispredictPenalty", ','); in EmitProcessorModels()
1476 (PM.ModelDef ? PM.ModelDef->getValueAsBit("PostRAScheduler") : false); in EmitProcessorModels()
1482 (PM.ModelDef ? PM.ModelDef->getValueAsBit("CompleteModel") : false); in EmitProcessorModels()
1488 (PM.ModelDef ? PM.ModelDef->getValueAsBit("EnableIntervals") : false); in EmitProcessorModels()