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1 //===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
64 /// CodeGenSubRegIndex - Represents a sub-register index.
80 // Are all super-registers containing this SubRegIndex covered by their
81 // sub-registers?
105 return I == Composed.end() ? nullptr : I->second; in compose()
117 // B->Offset == -1. For the other cases, accumulate the offset and set in addComposite()
125 SubRegRange &Range = this->Range.get(M); in addComposite()
126 SubRegRange &ARange = A->Range.get(M); in addComposite()
127 SubRegRange &BRange = B->Range.get(M); in addComposite()
129 if (Range.Offset != (uint16_t)-1 && ARange.Offset != (uint16_t)-1 && in addComposite()
130 BRange.Offset == (uint16_t)-1) { in addComposite()
137 SubRegRange &Range = this->Range.get(DefaultMode); in addComposite()
138 SubRegRange &ARange = A->Range.get(DefaultMode); in addComposite()
139 SubRegRange &BRange = B->Range.get(DefaultMode); in addComposite()
140 if (Range.Offset != (uint16_t)-1 && ARange.Offset != (uint16_t)-1 && in addComposite()
141 BRange.Offset == (uint16_t)-1) { in addComposite()
146 return (Ins.second || Ins.first->second == B) ? nullptr : Ins.first->second; in addComposite()
165 return this->EnumValue < RHS.EnumValue;
172 /// CodeGenRegister - Represents a register definition.
183 // Map SubRegIndex -> Register.
195 // Lazily compute a map of all sub-registers.
196 // This includes unique entries for all sub-sub-registers.
199 // Compute extra sub-registers by combining the existing sub-registers.
202 // Add this as a super-register to all sub-registers after the sub-register
207 assert(SubRegsComplete && "Must precompute sub-registers"); in getSubRegs()
211 // Add sub-registers to OSet following a pre-order defined by the .td file.
215 // Return the sub-register index naming Reg as a sub-register of this
216 // register. Returns NULL if Reg is not a sub-register.
223 // Get the list of super-registers in topological order, small to large.
227 assert(SubRegsComplete && "Must precompute sub-registers"); in getSuperRegs()
240 // identical sub-register structure. That is, they support the same set of
241 // sub-register indices mapping to the same kind of sub-registers
242 // (TopoSig-wise).
276 void adoptRegUnit(unsigned RUID) { RegUnits.set(RUID); } in adoptRegUnit()
281 // Canonically ordered set.
289 // The sub-registers explicit in the .td file form a tree.
296 // Super-registers where this is the first explicit sub-register.
318 // Bit mask of sub-classes including this, indexed by their EnumValue.
320 // List of super-classes, topologocally ordered to have the larger classes
327 // super-class.
330 // Map SubRegIndex -> sub-class. This is the largest sub-class where all
331 // registers have a SubRegIndex sub-register.
335 // Map SubRegIndex -> set of super-reg classes. This is all register
365 /// Generate register pressure set for this register class and any class
392 // RC is a sub-class of this class if it is a valid replacement for any
401 return SubClasses.test(RC->EnumValue); in hasSubClass()
404 // getSubClassWithSubReg - Returns the largest sub-class where all
405 // registers have a SubIdx sub-register.
430 // getSuperRegClasses - Returns a bit vector of all register classes
431 // containing only SubIdx super-registers of this class.
435 // addSuperRegClass - Add a class containing only SubIdx super-registers.
441 // getSubClasses - Returns a constant BitVector of subclasses indexed by
446 // getSuperClasses - Returns a list of super classes ordered by EnumValue.
460 // Get the set of registers. This set contains the same registers as
470 // Populate a unique sorted list of units from a register set.
478 // sub-classes. Note the ordering provided by this key is not the same as
494 // Create a non-user defined register class.
502 if (TheDef && !TheDef->isValueUnset("BaseClassOrder")) in getBaseClassOrder()
503 return TheDef->getValueAsInt("BaseClassOrder"); in getBaseClassOrder()
532 // Normally, one register unit is created per leaf register. Non-leaf
533 // registers inherit the units of their sub-registers.
541 // set of registers containing this unit can be computed as the union of
542 // these two registers and their super-registers.
578 // CodeGenRegBank - Represent a target's registers and the relations between
602 // Includes native (0..NumNativeRegUnits-1) and adopted register units.
618 // Remember each unique set of register units. Initially, this contains a
619 // unique set for each register class. Simliar sets are coalesced with
631 // Give each register unit set an order based on sorting criteria.
640 // Create a synthetic sub-class if it is missing.
667 // Populate the Composite map from sub-register relationships.
670 // Compute a lane mask for each sub-register index.
685 // Sub-register indices. The first NumNamedIndices are defined by the user
686 // in the .td files. The rest are synthesized such that all sub-registers
699 // Find or create a sub-register index representing the A+B composition.
703 // Find or create a sub-register index representing the concatenation of
704 // non-overlapping sibling indices.
720 return Reg->EnumValue - 1; in getRegIndex()
729 // Others should simply use Reg->getTopoSig().
731 return TopoSigs.insert(std::pair(Id, TopoSigs.size())).first->second; in getTopoSig()
740 RU.Artificial = R0->Artificial;
742 RU.Artificial |= R1->Artificial;
743 return RegUnits.size() - 1;
746 // Create a new non-native register unit that can be adopted by a register
751 return RegUnits.size() - 1; in newRegUnit()
781 /// getRegisterClassForRegister - Find the register class that contains the
784 /// classes have a superset-subset relationship and the same set of types,
819 // Get a set of register unit IDs for a given dimension of pressure.
824 // The number of pressure set lists may be larget than the number of
831 // Get a list of pressure set IDs for a register class. Liveness of a
832 // register in this class impacts each pressure set in this list by the
839 // Computed derived records such as missing sub-register indices.
842 // Compute the set of registers completely covered by the registers in Regs.
843 // The returned BitVector will have a bit set for each register in Regs,
844 // all sub-registers, and all super-registers that are covered by the
847 // This is used to compute the mask of call-preserved registers from a list
848 // of callee-saves.
851 // Bit mask of lanes that cover their registers. A sub-register index whose
853 // another sub-register with the same or larger lane mask.
857 // (non-native) reg units.