Lines Matching full:nf
238 class VLSEGSched<int nf, int eew, string emul, bit forceMasked = 0> : SchedCommon<
239 [!cast<SchedWrite>("WriteVLSEG" #nf #"e" #eew #"_" #emul)],
242 class VLSEGSchedMC<int nf, int eew> : VLSEGSched<nf, eew, "WorstCase",
245 class VSSEGSched<int nf, int eew, string emul, bit forceMasked = 0> : SchedCommon<
246 [!cast<SchedWrite>("WriteVSSEG" # nf # "e" # eew # "_" # emul)],
249 class VSSEGSchedMC<int nf, int eew> : VSSEGSched<nf, eew, "WorstCase",
252 class VLSEGFFSched<int nf, int eew, string emul, bit forceMasked = 0> : SchedCommon<
253 [!cast<SchedWrite>("WriteVLSEGFF" # nf # "e" # eew # "_" # emul)],
256 class VLSEGFFSchedMC<int nf, int eew> : VLSEGFFSched<nf, eew, "WorstCase",
260 class VLSSEGSched<int nf, int eew, string emul, bit forceMasked = 0> : SchedCommon<
261 [!cast<SchedWrite>("WriteVLSSEG" #nf #"e" #eew #"_" #emul)],
264 class VLSSEGSchedMC<int nf, int eew> : VLSSEGSched<nf, eew, "WorstCase",
267 class VSSSEGSched<int nf, int eew, string emul, bit forceMasked = 0> : SchedCommon<
268 [!cast<SchedWrite>("WriteVSSSEG" #nf #"e" #eew #"_" #emul)],
272 class VSSSEGSchedMC<int nf, int eew> : VSSSEGSched<nf, eew, "WorstCase",
276 class VLXSEGSched<int nf, int eew, bit isOrdered, string emul,
278 [!cast<SchedWrite>("WriteVL" #!if(isOrdered, "O", "U") #"XSEG" #nf #"e" #eew #"_" #emul)],
282 class VLXSEGSchedMC<int nf, int eew, bit isOrdered>:
283 VLXSEGSched<nf, eew, isOrdered, "WorstCase", forceMasked=1>;
286 class VSXSEGSched<int nf, int eew, bit isOrdered, string emul,
288 [!cast<SchedWrite>("WriteVS" #!if(isOrdered, "O", "U") #"XSEG" #nf #"e" #eew #"_" #emul)],
293 class VSXSEGSchedMC<int nf, int eew, bit isOrdered>:
294 VSXSEGSched<nf, eew, isOrdered, "WorstCase", forceMasked=1>;
308 // unit-stride whole register load vl<nf>r.v vd, (rs1)
309 class VWholeLoad<bits<3> nf, RISCVWidth width, string opcodestr, RegisterClass VRC>
310 : RVInstVLU<nf, width.Value{3}, LUMOPUnitStrideWholeReg,
344 class VUnitStrideSegmentLoad<bits<3> nf, RISCVWidth width, string opcodestr>
345 : RVInstVLU<nf, width.Value{3}, LUMOPUnitStride, width.Value{2-0},
350 class VUnitStrideSegmentLoadFF<bits<3> nf, RISCVWidth width, string opcodestr>
351 : RVInstVLU<nf, width.Value{3}, LUMOPUnitStrideFF, width.Value{2-0},
356 class VStridedSegmentLoad<bits<3> nf, RISCVWidth width, string opcodestr>
357 : RVInstVLS<nf, width.Value{3}, width.Value{2-0},
363 class VIndexedSegmentLoad<bits<3> nf, RISCVMOP mop, RISCVWidth width,
365 : RVInstVLX<nf, width.Value{3}, mop, width.Value{2-0},
379 // vs<nf>r.v vd, (rs1)
380 class VWholeStore<bits<3> nf, string opcodestr, RegisterClass VRC>
381 : RVInstVSU<nf, 0, SUMOPUnitStrideWholeReg,
407 class VUnitStrideSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr>
408 : RVInstVSU<nf, width.Value{3}, SUMOPUnitStride, width.Value{2-0},
413 class VStridedSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr>
414 : RVInstVSS<nf, width.Value{3}, width.Value{2-0}, (outs),
419 class VIndexedSegmentStore<bits<3> nf, RISCVMOP mop, RISCVWidth width,
421 : RVInstVSX<nf, width.Value{3}, mop, width.Value{2-0}, (outs),
1014 multiclass VWholeLoadN<int l, bits<3> nf, string opcodestr, RegisterClass VRC> {
1016 defvar s = !cast<SchedWrite>("WriteVLD" # !add(nf, 1) # "R");
1018 def E # l # _V : VWholeLoad<nf, w, opcodestr # "e" # l # ".v", VRC>,
1709 foreach nf=2-8 in {
1713 def VLSEG#nf#E#eew#_V :
1714 VUnitStrideSegmentLoad<!add(nf, -1), w, "vlseg"#nf#"e"#eew#".v">,
1715 VLSEGSchedMC<nf, eew>;
1716 def VLSEG#nf#E#eew#FF_V :
1717 VUnitStrideSegmentLoadFF<!add(nf, -1), w, "vlseg"#nf#"e"#eew#"ff.v">,
1718 VLSEGFFSchedMC<nf, eew>;
1719 def VSSEG#nf#E#eew#_V :
1720 VUnitStrideSegmentStore<!add(nf, -1), w, "vsseg"#nf#"e"#eew#".v">,
1721 VSSEGSchedMC<nf, eew>;
1723 def VLSSEG#nf#E#eew#_V :
1724 VStridedSegmentLoad<!add(nf, -1), w, "vlsseg"#nf#"e"#eew#".v">,
1725 VLSSEGSchedMC<nf, eew>;
1726 def VSSSEG#nf#E#eew#_V :
1727 VStridedSegmentStore<!add(nf, -1), w, "vssseg"#nf#"e"#eew#".v">,
1728 VSSSEGSchedMC<nf, eew>;
1731 def VLUXSEG#nf#EI#eew#_V :
1732 VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord, w,
1733 "vluxseg"#nf#"ei"#eew#".v">,
1734 VLXSEGSchedMC<nf, eew, isOrdered=0>;
1735 def VLOXSEG#nf#EI#eew#_V :
1736 VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder, w,
1737 "vloxseg"#nf#"ei"#eew#".v">,
1738 VLXSEGSchedMC<nf, eew, isOrdered=1>;
1739 def VSUXSEG#nf#EI#eew#_V :
1740 VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord, w,
1741 "vsuxseg"#nf#"ei"#eew#".v">,
1742 VSXSEGSchedMC<nf, eew, isOrdered=0>;
1743 def VSOXSEG#nf#EI#eew#_V :
1744 VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, w,
1745 "vsoxseg"#nf#"ei"#eew#".v">,
1746 VSXSEGSchedMC<nf, eew, isOrdered=1>;
1752 foreach nf=2-8 in {
1754 def VLSEG#nf#E64_V :
1755 VUnitStrideSegmentLoad<!add(nf, -1), LSWidth64, "vlseg"#nf#"e64.v">,
1756 VLSEGSchedMC<nf, 64>;
1757 def VLSEG#nf#E64FF_V :
1758 VUnitStrideSegmentLoadFF<!add(nf, -1), LSWidth64, "vlseg"#nf#"e64ff.v">,
1759 VLSEGFFSchedMC<nf, 64>;
1760 def VSSEG#nf#E64_V :
1761 VUnitStrideSegmentStore<!add(nf, -1), LSWidth64, "vsseg"#nf#"e64.v">,
1762 VSSEGSchedMC<nf, 64>;
1765 def VLSSEG#nf#E64_V :
1766 VStridedSegmentLoad<!add(nf, -1), LSWidth64, "vlsseg"#nf#"e64.v">,
1767 VLSSEGSchedMC<nf, 64>;
1768 def VSSSEG#nf#E64_V :
1769 VStridedSegmentStore<!add(nf, -1), LSWidth64, "vssseg"#nf#"e64.v">,
1770 VSSSEGSchedMC<nf, 64>;
1774 foreach nf = 2 - 8 in {
1776 def VLUXSEG #nf #EI64_V
1777 : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord, LSWidth64,
1778 "vluxseg" #nf #"ei64.v">,
1779 VLXSEGSchedMC<nf, 64, isOrdered=0>;
1780 def VLOXSEG #nf #EI64_V
1781 : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder, LSWidth64,
1782 "vloxseg" #nf #"ei64.v">,
1783 VLXSEGSchedMC<nf, 64, isOrdered=1>;
1784 def VSUXSEG #nf #EI64_V
1785 : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord, LSWidth64,
1786 "vsuxseg" #nf #"ei64.v">,
1787 VSXSEGSchedMC<nf, 64, isOrdered=0>;
1788 def VSOXSEG #nf #EI64_V
1789 : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, LSWidth64,
1790 "vsoxseg" #nf #"ei64.v">,
1791 VSXSEGSchedMC<nf, 64, isOrdered=1>;