Lines Matching +full:6 +full:v
1 //===-- RISCVInstrInfoV.td - RISC-V 'V' instructions -------*- tablegen -*-===//
9 /// This file describes the RISC-V instructions from the standard 'V' Vector
178 [!cast<SchedWrite>("WriteVMov" # n # "V")],
179 [!cast<SchedRead>("ReadVMov" # n # "V")]
308 // unit-stride whole register load vl<nf>r.v vd, (rs1)
379 // vs<nf>r.v vd, (rs1)
428 class VALUVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
434 class VALUmVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
442 class VALUrVV<bits<6> funct6, RISCVVFormat opv, string opcodestr,
452 class VALUVVNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr>
460 class VALUVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
466 class VALUmVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
474 class VALUrVX<bits<6> funct6, RISCVVFormat opv, string opcodestr,
484 class VALUVXNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr>
492 class VALUVI<bits<6> funct6, string opcodestr, Operand optype = simm5>
498 class VALUmVI<bits<6> funct6, string opcodestr, Operand optype = simm5>
506 class VALUVINoVm<bits<6> funct6, string opcodestr, Operand optype = simm5>
514 class VALUVF<bits<6> funct6, RISCVVFormat opv, string opcodestr>
520 class VALUrVF<bits<6> funct6, RISCVVFormat opv, string opcodestr,
530 class VALUVs2<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr>
545 VIndexedLoad<MOPLDIndexedUnord, w, "vluxei" # eew # ".v">,
548 VIndexedLoad<MOPLDIndexedOrder, w, "vloxei" # eew # ".v">,
552 VIndexedStore<MOPSTIndexedUnord, w, "vsuxei" # eew # ".v">,
555 VIndexedStore<MOPSTIndexedOrder, w, "vsoxei" # eew # ".v">,
559 multiclass VALU_IV_V<string opcodestr, bits<6> funct6> {
560 def V : VALUVV<funct6, OPIVV, opcodestr # ".vv">,
564 multiclass VALU_IV_X<string opcodestr, bits<6> funct6> {
569 multiclass VALU_IV_I<string opcodestr, bits<6> funct6> {
574 multiclass VALU_IV_V_X_I<string opcodestr, bits<6> funct6>
579 multiclass VALU_IV_V_X<string opcodestr, bits<6> funct6>
583 multiclass VALU_IV_X_I<string opcodestr, bits<6> funct6>
587 multiclass VALU_MV_V_X<string opcodestr, bits<6> funct6, string vw> {
588 def V : VALUVV<funct6, OPMVV, opcodestr # "." # vw # "v">,
594 multiclass VMAC_MV_V_X<string opcodestr, bits<6> funct6> {
595 def V : VALUrVV<funct6, OPMVV, opcodestr # ".vv">,
603 multiclass VWMAC_MV_X<string opcodestr, bits<6> funct6> {
610 multiclass VWMAC_MV_V_X<string opcodestr, bits<6> funct6>
613 def V : VALUrVV<funct6, OPMVV, opcodestr # ".vv", EarlyClobber=1>,
618 multiclass VALU_MV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
623 multiclass VMRG_IV_V_X_I<string opcodestr, bits<6> funct6> {
632 multiclass VALUm_IV_V_X<string opcodestr, bits<6> funct6> {
639 multiclass VALUm_IV_V_X_I<string opcodestr, bits<6> funct6>
645 multiclass VALUNoVm_IV_V_X<string opcodestr, bits<6> funct6> {
646 def V : VALUVVNoVm<funct6, OPIVV, opcodestr # ".vv">,
654 multiclass VALUNoVm_IV_V_X_I<string opcodestr, bits<6> funct6>
660 multiclass VALU_FV_F<string opcodestr, bits<6> funct6> {
665 multiclass VALU_FV_V_F<string opcodestr, bits<6> funct6>
667 def V : VALUVV<funct6, OPFVV, opcodestr # ".vv">,
671 multiclass VWALU_FV_V_F<string opcodestr, bits<6> funct6, string vw> {
672 def V : VALUVV<funct6, OPFVV, opcodestr # "." # vw # "v">,
678 multiclass VMUL_FV_V_F<string opcodestr, bits<6> funct6> {
679 def V : VALUVV<funct6, OPFVV, opcodestr # ".vv">,
685 multiclass VDIV_FV_F<string opcodestr, bits<6> funct6> {
690 multiclass VDIV_FV_V_F<string opcodestr, bits<6> funct6>
692 def V : VALUVV<funct6, OPFVV, opcodestr # ".vv">,
696 multiclass VWMUL_FV_V_F<string opcodestr, bits<6> funct6> {
697 def V : VALUVV<funct6, OPFVV, opcodestr # ".vv">,
703 multiclass VMAC_FV_V_F<string opcodestr, bits<6> funct6> {
704 def V : VALUrVV<funct6, OPFVV, opcodestr # ".vv">,
712 multiclass VWMAC_FV_V_F<string opcodestr, bits<6> funct6> {
714 def V : VALUrVV<funct6, OPFVV, opcodestr # ".vv", EarlyClobber=1>,
723 multiclass VSQR_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
728 multiclass VRCP_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
733 multiclass VMINMAX_FV_V_F<string opcodestr, bits<6> funct6> {
734 def V : VALUVV<funct6, OPFVV, opcodestr # ".vv">,
740 multiclass VCMP_FV_F<string opcodestr, bits<6> funct6> {
745 multiclass VCMP_FV_V_F<string opcodestr, bits<6> funct6>
747 def V : VALUVV<funct6, OPFVV, opcodestr # ".vv">,
751 multiclass VSGNJ_FV_V_F<string opcodestr, bits<6> funct6> {
752 def V : VALUVV<funct6, OPFVV, opcodestr # ".vv">,
758 multiclass VCLS_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
763 multiclass VCVTF_IV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
768 multiclass VCVTI_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
773 multiclass VWCVTF_IV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
778 multiclass VWCVTI_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
783 multiclass VWCVTF_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
788 multiclass VNCVTF_IV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
793 multiclass VNCVTI_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
798 multiclass VNCVTF_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
803 multiclass VRED_MV_V<string opcodestr, bits<6> funct6> {
808 multiclass VREDMINMAX_MV_V<string opcodestr, bits<6> funct6> {
813 multiclass VWRED_IV_V<string opcodestr, bits<6> funct6> {
818 multiclass VRED_FV_V<string opcodestr, bits<6> funct6> {
823 multiclass VREDMINMAX_FV_V<string opcodestr, bits<6> funct6> {
828 multiclass VREDO_FV_V<string opcodestr, bits<6> funct6> {
833 multiclass VWRED_FV_V<string opcodestr, bits<6> funct6> {
838 multiclass VWREDO_FV_V<string opcodestr, bits<6> funct6> {
843 multiclass VMALU_MV_Mask<string opcodestr, bits<6> funct6, string vm = "v"> {
849 multiclass VMSFS_MV_V<string opcodestr, bits<6> funct6, bits<5> vs1> {
854 multiclass VIOTA_MV_V<string opcodestr, bits<6> funct6, bits<5> vs1> {
859 multiclass VSHT_IV_V_X_I<string opcodestr, bits<6> funct6> {
860 def V : VALUVV<funct6, OPIVV, opcodestr # ".vv">,
868 multiclass VNSHT_IV_V_X_I<string opcodestr, bits<6> funct6> {
869 def V : VALUVV<funct6, OPIVV, opcodestr # ".wv">,
877 multiclass VMINMAX_IV_V_X<string opcodestr, bits<6> funct6> {
878 def V : VALUVV<funct6, OPIVV, opcodestr # ".vv">,
884 multiclass VCMP_IV_V<string opcodestr, bits<6> funct6> {
885 def V : VALUVV<funct6, OPIVV, opcodestr # ".vv">,
889 multiclass VCMP_IV_X<string opcodestr, bits<6> funct6> {
894 multiclass VCMP_IV_I<string opcodestr, bits<6> funct6> {
899 multiclass VCMP_IV_V_X_I<string opcodestr, bits<6> funct6>
904 multiclass VCMP_IV_X_I<string opcodestr, bits<6> funct6>
908 multiclass VCMP_IV_V_X<string opcodestr, bits<6> funct6>
912 multiclass VMUL_MV_V_X<string opcodestr, bits<6> funct6> {
913 def V : VALUVV<funct6, OPMVV, opcodestr # ".vv">,
919 multiclass VWMUL_MV_V_X<string opcodestr, bits<6> funct6> {
920 def V : VALUVV<funct6, OPMVV, opcodestr # ".vv">,
926 multiclass VDIV_MV_V_X<string opcodestr, bits<6> funct6> {
927 def V : VALUVV<funct6, OPMVV, opcodestr # ".vv">,
933 multiclass VSALU_IV_V_X<string opcodestr, bits<6> funct6> {
934 def V : VALUVV<funct6, OPIVV, opcodestr # ".vv">,
940 multiclass VSALU_IV_V_X_I<string opcodestr, bits<6> funct6>
946 multiclass VAALU_MV_V_X<string opcodestr, bits<6> funct6> {
947 def V : VALUVV<funct6, OPMVV, opcodestr # ".vv">,
953 multiclass VSMUL_IV_V_X<string opcodestr, bits<6> funct6> {
954 def V : VALUVV<funct6, OPIVV, opcodestr # ".vv">,
960 multiclass VSSHF_IV_V_X_I<string opcodestr, bits<6> funct6> {
961 def V : VALUVV<funct6, OPIVV, opcodestr # ".vv">,
969 multiclass VNCLP_IV_V_X_I<string opcodestr, bits<6> funct6> {
970 def V : VALUVV<funct6, OPIVV, opcodestr # ".wv">,
978 multiclass VSLD_IV_X_I<string opcodestr, bits<6> funct6, bit slidesUp> {
988 multiclass VSLD1_MV_X<string opcodestr, bits<6> funct6> {
993 multiclass VSLD1_FV_F<string opcodestr, bits<6> funct6> {
998 multiclass VGTR_IV_V_X_I<string opcodestr, bits<6> funct6> {
999 def V : VALUVV<funct6, OPIVV, opcodestr # ".vv">,
1009 multiclass VCPR_MV_Mask<string opcodestr, bits<6> funct6, string vm = "v"> {
1018 def E # l # _V : VWholeLoad<nf, w, opcodestr # "e" # l # ".v", VRC>,
1047 def VLE#eew#_V : VUnitStrideLoad<w, "vle"#eew#".v">, VLESchedMC;
1048 def VSE#eew#_V : VUnitStrideStore<w, "vse"#eew#".v">, VSESchedMC;
1051 def VLE#eew#FF_V : VUnitStrideLoadFF<w, "vle"#eew#"ff.v">, VLFSchedMC;
1054 def VLSE#eew#_V : VStridedLoad<w, "vlse"#eew#".v">, VLSSchedMC<eew>;
1055 def VSSE#eew#_V : VStridedStore<w, "vsse"#eew#".v">, VSSSchedMC<eew>;
1069 def VLM_V : VUnitStrideLoadMask<"vlm.v">,
1071 def VSM_V : VUnitStrideStoreMask<"vsm.v">,
1073 def : InstAlias<"vle1.v $vd, (${rs1})",
1075 def : InstAlias<"vse1.v $vs3, (${rs1})",
1078 def VS1R_V : VWholeStore<0, "vs1r.v", VR>,
1080 def VS2R_V : VWholeStore<1, "vs2r.v", VRM2>,
1082 def VS4R_V : VWholeStore<3, "vs4r.v", VRM4>,
1084 def VS8R_V : VWholeStore<7, "vs8r.v", VRM8>,
1087 def : InstAlias<"vl1r.v $vd, (${rs1})", (VL1RE8_V VR:$vd, GPR:$rs1)>;
1088 def : InstAlias<"vl2r.v $vd, (${rs1})", (VL2RE8_V VRM2:$vd, GPR:$rs1)>;
1089 def : InstAlias<"vl4r.v $vd, (${rs1})", (VL4RE8_V VRM4:$vd, GPR:$rs1)>;
1090 def : InstAlias<"vl8r.v $vd, (${rs1})", (VL8RE8_V VRM8:$vd, GPR:$rs1)>;
1099 def : InstAlias<"vneg.v $vd, $vs$vm", (VRSUB_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>;
1100 def : InstAlias<"vneg.v $vd, $vs", (VRSUB_VX VR:$vd, VR:$vs, X0, zero_reg)>;
1109 defm VWADDU_V : VALU_MV_V_X<"vwaddu", 0b110000, "v">;
1110 defm VWSUBU_V : VALU_MV_V_X<"vwsubu", 0b110010, "v">;
1111 defm VWADD_V : VALU_MV_V_X<"vwadd", 0b110001, "v">;
1112 defm VWSUB_V : VALU_MV_V_X<"vwsub", 0b110011, "v">;
1126 def : InstAlias<"vwcvt.x.x.v $vd, $vs$vm",
1128 def : InstAlias<"vwcvt.x.x.v $vd, $vs",
1130 def : InstAlias<"vwcvtu.x.x.v $vd, $vs$vm",
1132 def : InstAlias<"vwcvtu.x.x.v $vd, $vs",
1160 def : InstAlias<"vnot.v $vd, $vs$vm",
1162 def : InstAlias<"vnot.v $vd, $vs",
1296 (ins VR:$vs1), "vmv.v.v", "$vd, $vs1">,
1300 (ins GPR:$rs1), "vmv.v.x", "$vd, $rs1">,
1304 (ins simm5:$imm), "vmv.v.i", "$vd, $imm">,
1347 defm VFWADD_V : VWALU_FV_V_F<"vfwadd", 0b110000, "v">;
1348 defm VFWSUB_V : VWALU_FV_V_F<"vfwsub", 0b110010, "v">;
1395 defm VFSQRT_V : VSQR_FV_VS2<"vfsqrt.v", 0b010011, 0b00000>;
1396 defm VFREC7_V : VRCP_FV_VS2<"vfrec7.v", 0b010011, 0b00101>;
1400 defm VFRSQRT7_V : VRCP_FV_VS2<"vfrsqrt7.v", 0b010011, 0b00100>;
1413 def : InstAlias<"vfneg.v $vd, $vs$vm",
1415 def : InstAlias<"vfneg.v $vd, $vs",
1417 def : InstAlias<"vfabs.v $vd, $vs$vm",
1419 def : InstAlias<"vfabs.v $vd, $vs",
1438 defm VFCLASS_V : VCLS_FV_VS2<"vfclass.v", 0b010011, 0b10000>;
1453 (ins FPR32:$rs1), "vfmv.v.f", "$vd, $rs1">,
1461 defm VFCVT_XU_F_V : VCVTI_FV_VS2<"vfcvt.xu.f.v", 0b010010, 0b00000>;
1462 defm VFCVT_X_F_V : VCVTI_FV_VS2<"vfcvt.x.f.v", 0b010010, 0b00001>;
1464 defm VFCVT_RTZ_XU_F_V : VCVTI_FV_VS2<"vfcvt.rtz.xu.f.v", 0b010010, 0b00110>;
1465 defm VFCVT_RTZ_X_F_V : VCVTI_FV_VS2<"vfcvt.rtz.x.f.v", 0b010010, 0b00111>;
1467 defm VFCVT_F_XU_V : VCVTF_IV_VS2<"vfcvt.f.xu.v", 0b010010, 0b00010>;
1468 defm VFCVT_F_X_V : VCVTF_IV_VS2<"vfcvt.f.x.v", 0b010010, 0b00011>;
1476 defm VFWCVT_XU_F_V : VWCVTI_FV_VS2<"vfwcvt.xu.f.v", 0b010010, 0b01000>;
1477 defm VFWCVT_X_F_V : VWCVTI_FV_VS2<"vfwcvt.x.f.v", 0b010010, 0b01001>;
1479 defm VFWCVT_RTZ_XU_F_V : VWCVTI_FV_VS2<"vfwcvt.rtz.xu.f.v", 0b010010, 0b01110>;
1480 defm VFWCVT_RTZ_X_F_V : VWCVTI_FV_VS2<"vfwcvt.rtz.x.f.v", 0b010010, 0b01111>;
1481 defm VFWCVT_F_XU_V : VWCVTF_IV_VS2<"vfwcvt.f.xu.v", 0b010010, 0b01010>;
1482 defm VFWCVT_F_X_V : VWCVTF_IV_VS2<"vfwcvt.f.x.v", 0b010010, 0b01011>;
1483 defm VFWCVT_F_F_V : VWCVTF_FV_VS2<"vfwcvt.f.f.v", 0b010010, 0b01100>;
1626 (ins VMaskOp:$vm), "vid.v", "$vd$vm">,
1699 (ins vrc:$vs2), "vmv" # n # "r.v", "$vd, $vs2">,
1714 VUnitStrideSegmentLoad<!add(nf, -1), w, "vlseg"#nf#"e"#eew#".v">,
1717 VUnitStrideSegmentLoadFF<!add(nf, -1), w, "vlseg"#nf#"e"#eew#"ff.v">,
1720 VUnitStrideSegmentStore<!add(nf, -1), w, "vsseg"#nf#"e"#eew#".v">,
1724 VStridedSegmentLoad<!add(nf, -1), w, "vlsseg"#nf#"e"#eew#".v">,
1727 VStridedSegmentStore<!add(nf, -1), w, "vssseg"#nf#"e"#eew#".v">,
1733 "vluxseg"#nf#"ei"#eew#".v">,
1737 "vloxseg"#nf#"ei"#eew#".v">,
1741 "vsuxseg"#nf#"ei"#eew#".v">,
1745 "vsoxseg"#nf#"ei"#eew#".v">,
1755 VUnitStrideSegmentLoad<!add(nf, -1), LSWidth64, "vlseg"#nf#"e64.v">,
1758 VUnitStrideSegmentLoadFF<!add(nf, -1), LSWidth64, "vlseg"#nf#"e64ff.v">,
1761 VUnitStrideSegmentStore<!add(nf, -1), LSWidth64, "vsseg"#nf#"e64.v">,
1766 VStridedSegmentLoad<!add(nf, -1), LSWidth64, "vlsseg"#nf#"e64.v">,
1769 VStridedSegmentStore<!add(nf, -1), LSWidth64, "vssseg"#nf#"e64.v">,
1778 "vluxseg" #nf #"ei64.v">,
1782 "vloxseg" #nf #"ei64.v">,
1786 "vsuxseg" #nf #"ei64.v">,
1790 "vsoxseg" #nf #"ei64.v">,