Lines Matching +full:5 +full:vs
60 def simm5 : RISCVSImmLeafOp<5> {
64 return isInt<5>(Imm);
76 [{return (isInt<5>(Imm) && Imm != -16) || Imm == 16;}]> {
82 return (isInt<5>(Imm) && Imm != -16) || Imm == 16;
88 [{return Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16);}]>;
379 // vs<nf>r.v vd, (rs1)
530 class VALUVs2<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr>
618 multiclass VALU_MV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
723 multiclass VSQR_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
728 multiclass VRCP_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
758 multiclass VCLS_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
763 multiclass VCVTF_IV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
768 multiclass VCVTI_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
773 multiclass VWCVTF_IV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
778 multiclass VWCVTI_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
783 multiclass VWCVTF_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
788 multiclass VNCVTF_IV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
793 multiclass VNCVTI_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
798 multiclass VNCVTF_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
804 def _VS : VALUVV<funct6, OPMVV, opcodestr # ".vs">,
809 def _VS : VALUVV<funct6, OPMVV, opcodestr # ".vs">,
814 def _VS : VALUVV<funct6, OPIVV, opcodestr # ".vs">,
819 def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs">,
824 def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs">,
829 def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs">,
834 def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs">,
839 def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs">,
849 multiclass VMSFS_MV_V<string opcodestr, bits<6> funct6, bits<5> vs1> {
854 multiclass VIOTA_MV_V<string opcodestr, bits<6> funct6, bits<5> vs1> {
1099 def : InstAlias<"vneg.v $vd, $vs$vm", (VRSUB_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>;
1100 def : InstAlias<"vneg.v $vd, $vs", (VRSUB_VX VR:$vd, VR:$vs, X0, zero_reg)>;
1126 def : InstAlias<"vwcvt.x.x.v $vd, $vs$vm",
1127 (VWADD_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>;
1128 def : InstAlias<"vwcvt.x.x.v $vd, $vs",
1129 (VWADD_VX VR:$vd, VR:$vs, X0, zero_reg)>;
1130 def : InstAlias<"vwcvtu.x.x.v $vd, $vs$vm",
1131 (VWADDU_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>;
1132 def : InstAlias<"vwcvtu.x.x.v $vd, $vs",
1133 (VWADDU_VX VR:$vd, VR:$vs, X0, zero_reg)>;
1160 def : InstAlias<"vnot.v $vd, $vs$vm",
1161 (VXOR_VI VR:$vd, VR:$vs, -1, VMaskOp:$vm)>;
1162 def : InstAlias<"vnot.v $vd, $vs",
1163 (VXOR_VI VR:$vd, VR:$vs, -1, zero_reg)>;
1180 def : InstAlias<"vncvt.x.x.w $vd, $vs$vm",
1181 (VNSRL_WX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>;
1182 def : InstAlias<"vncvt.x.x.w $vd, $vs",
1183 (VNSRL_WX VR:$vd, VR:$vs, X0, zero_reg)>;
1413 def : InstAlias<"vfneg.v $vd, $vs$vm",
1414 (VFSGNJN_VV VR:$vd, VR:$vs, VR:$vs, VMaskOp:$vm)>;
1415 def : InstAlias<"vfneg.v $vd, $vs",
1416 (VFSGNJN_VV VR:$vd, VR:$vs, VR:$vs, zero_reg)>;
1417 def : InstAlias<"vfabs.v $vd, $vs$vm",
1418 (VFSGNJX_VV VR:$vd, VR:$vs, VR:$vs, VMaskOp:$vm)>;
1419 def : InstAlias<"vfabs.v $vd, $vs",
1420 (VFSGNJX_VV VR:$vd, VR:$vs, VR:$vs, zero_reg)>;
1542 def : InstAlias<"vfredsum.vs $vd, $vs2, $vs1$vm",
1557 def : InstAlias<"vfwredsum.vs $vd, $vs2, $vs1$vm",
1574 def : InstAlias<"vmmv.m $vd, $vs",
1575 (VMAND_MM VR:$vd, VR:$vs, VR:$vs)>;
1580 def : InstAlias<"vmnot.m $vd, $vs",
1581 (VMNAND_MM VR:$vd, VR:$vs, VR:$vs)>;