Lines Matching full:mo
47 const MCOperand &MO = MI.getOperand(OpNo);
49 if (MO.isReg() || MO.isImm())
50 return getMachineOpValue(MI, MO, Fixups, STI);
53 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
157 const MCOperand &MO = MI.getOperand(OpNo);
158 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
161 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
170 const MCOperand &MO = MI.getOperand(OpNo);
171 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
174 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
183 const MCOperand &MO = MI.getOperand(OpNo);
184 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
187 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
205 const MCOperand &MO = MI.getOperand(OpNo);
206 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
209 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
218 const MCOperand &MO = MI.getOperand(OpNo);
219 assert(!MO.isReg() && "Not expecting a register for this operand.");
220 if (MO.isImm())
221 return getMachineOpValue(MI, MO, Fixups, STI);
224 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Fixup));
247 const MCOperand &MO = MI.getOperand(OpNo);
248 if (MO.isImm())
249 return getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF;
252 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
261 const MCOperand &MO = MI.getOperand(OpNo);
262 if (MO.isImm())
263 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF);
266 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
275 const MCOperand &MO = MI.getOperand(OpNo);
276 if (MO.isImm()) {
277 assert(!(MO.getImm() % 16) &&
279 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF);
283 Fixups.push_back(MCFixup::create(IsLittleEndian ? 0 : 2, MO.getExpr(),
294 const MCOperand &MO = MI.getOperand(OpNo);
296 assert(MO.isImm() && "Expecting an immediate operand.");
297 assert(!(MO.getImm() % 8) && "Expecting offset to be 8 byte aligned.");
299 unsigned DX = (MO.getImm() >> 3) & 0x3F;
317 const MCOperand &MO = MI.getOperand(OpNo);
318 if (!MO.isExpr())
319 return (getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL;
321 // At this point in the function it is known that MO is of type MCExpr.
324 const MCExpr *Expr = MO.getExpr();
391 const MCOperand &MO = MI.getOperand(OpNo);
392 return (getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL;
400 const MCOperand &MO = MI.getOperand(OpNo);
401 assert(MO.isImm());
402 return getMachineOpValue(MI, MO, Fixups, STI) >> 3;
410 const MCOperand &MO = MI.getOperand(OpNo);
411 assert(MO.isImm());
412 return getMachineOpValue(MI, MO, Fixups, STI) >> 2;
420 const MCOperand &MO = MI.getOperand(OpNo);
421 assert(MO.isImm());
422 return getMachineOpValue(MI, MO, Fixups, STI) >> 1;
428 const MCOperand &MO = MI.getOperand(OpNo);
429 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI);
435 const MCExpr *Expr = MO.getExpr();
451 const MCOperand &MO = MI.getOperand(OpNo+1);
452 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
461 const MCOperand &MO = MI.getOperand(OpNo);
464 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
465 return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
472 static unsigned getOpIdxForMO(const MCInst &MI, const MCOperand &MO) {
475 if (&Op == &MO)
483 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
486 if (MO.isReg()) {
491 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
492 unsigned OpNo = getOpIdxForMO(MI, MO);
494 PPC::getRegNumForOperand(MCII.get(MI.getOpcode()), MO.getReg(), OpNo);
498 assert(MO.isImm() &&
500 return MO.getImm();