102         {ISD::SHL, ISD::SRA, ISD::SRL, ISD::SETCC, ISD::VSELECT});  in MipsSETargetLowering()
338   setOperationAction(ISD::SHL, Ty, Legal);  in addMSAIntType()
804     return DAG.getNode(ISD::SHL, DL, VT, X,  in genConstMult()
905     if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {  in performSRACombine()
1038   case ISD::SHL:  in PerformDAGCombine()
1495     Exp2Imm = DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, DL, VecTy),  in lowerMSABinaryBitImmIntr()
1519   SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, truncateVecElts(Op, DAG));  in lowerMSABitClear()
1654                        DAG.getNode(ISD::SHL, DL, VecTy, One,  in lowerINTRINSIC_WO_CHAIN()
1690                        DAG.getNode(ISD::SHL, DL, VecTy, One,  in lowerINTRINSIC_WO_CHAIN()
1988                        DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,  in lowerINTRINSIC_WO_CHAIN()
2171     return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),  in lowerINTRINSIC_WO_CHAIN()
2177     return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),  in lowerINTRINSIC_WO_CHAIN()