Lines Matching refs:Op0Op0
611 SDValue Op0Op0 = Op0->getOperand(0); in performORCombine() local
625 if (isVSplat(Op0Op0, Mask, IsLittleEndian)) { in performORCombine()
626 Cond = Op0Op0; in performORCombine()
644 IfSet = Op0Op0; in performORCombine()
660 if (isBitwiseInverse(Op0Op0, Op1Op0)) { in performORCombine()
667 IfClr = Op0Op0; in performORCombine()
668 } else if (isBitwiseInverse(Op0Op0, Op1Op1)) { in performORCombine()
675 IfClr = Op0Op0; in performORCombine()
676 } else if (isBitwiseInverse(Op1Op0, Op0Op0)) { in performORCombine()
677 Cond = Op0Op0; in performORCombine()
680 } else if (isBitwiseInverse(Op1Op1, Op0Op0)) { in performORCombine()
681 Cond = Op0Op0; in performORCombine()
686 IfSet = Op0Op0; in performORCombine()
690 IfSet = Op0Op0; in performORCombine()
906 SDValue Op0Op0 = Op0->getOperand(0); in performSRACombine() local
912 if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT && in performSRACombine()
913 Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT) in performSRACombine()
916 EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT(); in performSRACombine()
920 (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT && in performSRACombine()
922 SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1), in performSRACombine()
923 Op0Op0->getOperand(2) }; in performSRACombine()
924 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, SDLoc(Op0Op0), in performSRACombine()
925 Op0Op0->getVTList(), in performSRACombine()
926 ArrayRef(Ops, Op0Op0->getNumOperands())); in performSRACombine()