Lines Matching refs:IntRegs
10 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
11 (MI HvxVR:$src1, IntRegs:$src2)>;
12 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, IntRegs:$src2),
13 (MI HvxVR:$src1, IntRegs:$src2)>;
47 def: Pat<(IntID HvxWR:$src1, IntRegs:$src2),
48 (MI HvxWR:$src1, IntRegs:$src2)>;
49 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, IntRegs:$src2),
50 (MI HvxWR:$src1, IntRegs:$src2)>;
54 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),
55 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
57 IntRegs:$src3),
58 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
62 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),
63 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
65 IntRegs:$src3),
66 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
70 def: Pat<(IntID HvxQR:$src1, IntRegs:$src2),
71 (MI HvxQR:$src1, IntRegs:$src2)>;
72 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, IntRegs:$src2),
73 (MI HvxQR:$src1, IntRegs:$src2)>;
77 def: Pat<(IntID HvxVR:$src1, HvxQR:$src2, IntRegs:$src3),
78 (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>;
80 IntRegs:$src3),
81 (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>;
92 def: Pat<(IntID IntRegs:$src1),
93 (MI IntRegs:$src1)>;
94 def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1),
95 (MI IntRegs:$src1)>;