Lines Matching full:src1
10 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
11 (MI HvxVR:$src1, IntRegs:$src2)>;
12 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, IntRegs:$src2),
13 (MI HvxVR:$src1, IntRegs:$src2)>;
17 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),
18 (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
19 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
21 (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
25 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
26 (MI HvxVR:$src1, HvxVR:$src2)>;
27 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2),
28 (MI HvxVR:$src1, HvxVR:$src2)>;
32 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2),
33 (MI HvxWR:$src1, HvxWR:$src2)>;
34 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2),
35 (MI HvxWR:$src1, HvxWR:$src2)>;
39 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),
40 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
41 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
43 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
47 def: Pat<(IntID HvxWR:$src1, IntRegs:$src2),
48 (MI HvxWR:$src1, IntRegs:$src2)>;
49 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, IntRegs:$src2),
50 (MI HvxWR:$src1, IntRegs:$src2)>;
54 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),
55 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
56 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2,
58 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
62 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),
63 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
64 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
66 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
70 def: Pat<(IntID HvxQR:$src1, IntRegs:$src2),
71 (MI HvxQR:$src1, IntRegs:$src2)>;
72 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, IntRegs:$src2),
73 (MI HvxQR:$src1, IntRegs:$src2)>;
77 def: Pat<(IntID HvxVR:$src1, HvxQR:$src2, IntRegs:$src3),
78 (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>;
79 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxQR:$src2,
81 (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>;
85 def: Pat<(IntID HvxQR:$src1, HvxVR:$src2),
86 (MI HvxQR:$src1, HvxVR:$src2)>;
87 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxVR:$src2),
88 (MI HvxQR:$src1, HvxVR:$src2)>;
92 def: Pat<(IntID IntRegs:$src1),
93 (MI IntRegs:$src1)>;
94 def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1),
95 (MI IntRegs:$src1)>;
99 def: Pat<(IntID HvxQR:$src1, HvxQR:$src2),
100 (MI HvxQR:$src1, HvxQR:$src2)>;
101 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxQR:$src2),
102 (MI HvxQR:$src1, HvxQR:$src2)>;
106 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, imm:$src3),
107 (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>;
108 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
110 (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>;
114 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4),
115 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
116 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
118 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
122 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4),
123 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;
124 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
126 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4)>;