Lines Matching +full:8 +full:kb
56 GISelKnownBits &KB, GISelCSEInfo *CSEInfo,
132 GISelKnownBits &KB, GISelCSEInfo *CSEInfo, in AMDGPUPostLegalizerCombinerImpl() argument
135 : Combiner(MF, CInfo, TPC, &KB, CSEInfo), RuleConfig(RuleConfig), STI(STI), in AMDGPUPostLegalizerCombinerImpl()
137 Helper(Observer, B, /*IsPreLegalize*/ false, &KB, MDT, LI), in AMDGPUPostLegalizerCombinerImpl()
220 const APInt Mask = APInt::getHighBitsSet(SrcSize, SrcSize - 8); in matchUCharToFloat()
330 unsigned ShiftOffset = 8 * Offset; in matchCvtF32UByteN()
338 return ShiftOffset < 32 && ShiftOffset >= 8 && (ShiftOffset % 8) == 0; in matchCvtF32UByteN()
347 unsigned NewOpc = AMDGPU::G_AMDGPU_CVT_F32_UBYTE0 + MatchInfo.ShiftOffset / 8; in applyCvtF32UByteN()
353 assert(SrcTy.isScalar() && SrcTy.getSizeInBits() >= 8); in applyCvtF32UByteN()
389 return Width == 8; in matchCombineSignExtendInReg()
395 return Width == 8; in matchCombineSignExtendInReg()
424 if (KB->getKnownBits(Src1).countMinLeadingZeros() >= 32 && in matchCombine_s_mul_u64()
425 KB->getKnownBits(Src0).countMinLeadingZeros() >= 32) { in matchCombine_s_mul_u64()
430 if (KB->computeNumSignBits(Src1) >= 33 && in matchCombine_s_mul_u64()
431 KB->computeNumSignBits(Src0) >= 33) { in matchCombine_s_mul_u64()
495 GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF); in runOnMachineFunction() local
503 AMDGPUPostLegalizerCombinerImpl Impl(MF, CInfo, TPC, *KB, /*CSEInfo*/ nullptr, in runOnMachineFunction()