Lines Matching refs:BCSrc
687 SDValue BCSrc = N->getOperand(0); in fnegFoldsIntoOp() local
688 if (BCSrc.getOpcode() == ISD::BUILD_VECTOR) { in fnegFoldsIntoOp()
689 return BCSrc.getNumOperands() == 2 && in fnegFoldsIntoOp()
690 BCSrc.getOperand(1).getValueSizeInBits() == 32; in fnegFoldsIntoOp()
693 return BCSrc.getOpcode() == ISD::SELECT && BCSrc.getValueType() == MVT::f32; in fnegFoldsIntoOp()
4948 SDValue BCSrc = N0.getOperand(0); in performFNegCombine() local
4949 if (BCSrc.getOpcode() == ISD::BUILD_VECTOR) { in performFNegCombine()
4950 SDValue HighBits = BCSrc.getOperand(BCSrc.getNumOperands() - 1); in performFNegCombine()
4969 SmallVector<SDValue, 8> Ops(BCSrc->op_begin(), BCSrc->op_end()); in performFNegCombine()
4973 DAG.getNode(ISD::BUILD_VECTOR, SL, BCSrc.getValueType(), Ops); in performFNegCombine()
4981 if (BCSrc.getOpcode() == ISD::SELECT && VT == MVT::f32 && in performFNegCombine()
4982 BCSrc.hasOneUse()) { in performFNegCombine()
4989 DAG.getNode(ISD::BITCAST, SL, MVT::f32, BCSrc.getOperand(1)); in performFNegCombine()
4991 DAG.getNode(ISD::BITCAST, SL, MVT::f32, BCSrc.getOperand(2)); in performFNegCombine()
4996 return DAG.getNode(ISD::SELECT, SL, MVT::f32, BCSrc.getOperand(0), NegLHS, in performFNegCombine()