Lines Matching full:sl
923 SDLoc SL(Op); in getNegatedExpression() local
928 return DAG.getNode(AMDGPUISD::RCP, SL, VT, NegSrc, Op->getFlags()); in getNegatedExpression()
1510 SDLoc SL(Op); in LowerCONCAT_VECTORS() local
1522 SDValue NewIn = DAG.getNode(ISD::BITCAST, SL, NewEltVT, In); in LowerCONCAT_VECTORS()
1531 SDValue BV = DAG.getBuildVector(NewVT, SL, Args); in LowerCONCAT_VECTORS()
1532 return DAG.getNode(ISD::BITCAST, SL, VT, BV); in LowerCONCAT_VECTORS()
1539 return DAG.getBuildVector(Op.getValueType(), SL, Args); in LowerCONCAT_VECTORS()
1544 SDLoc SL(Op); in LowerEXTRACT_SUBVECTOR() local
1560 SDValue Tmp = DAG.getNode(ISD::BITCAST, SL, NewSrcVT, Op.getOperand(0)); in LowerEXTRACT_SUBVECTOR()
1566 Tmp = DAG.getBuildVector(NewVT, SL, Args); in LowerEXTRACT_SUBVECTOR()
1568 return DAG.getNode(ISD::BITCAST, SL, VT, Tmp); in LowerEXTRACT_SUBVECTOR()
1574 return DAG.getBuildVector(Op.getValueType(), SL, Args); in LowerEXTRACT_SUBVECTOR()
1704 SDLoc SL(Op); in split64BitValue() local
1706 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in split64BitValue()
1708 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in split64BitValue()
1709 const SDValue One = DAG.getConstant(1, SL, MVT::i32); in split64BitValue()
1711 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in split64BitValue()
1712 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in split64BitValue()
1718 SDLoc SL(Op); in getLoHalf64() local
1720 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in getLoHalf64()
1721 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in getLoHalf64()
1722 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in getLoHalf64()
1726 SDLoc SL(Op); in getHiHalf64() local
1728 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in getHiHalf64()
1729 const SDValue One = DAG.getConstant(1, SL, MVT::i32); in getHiHalf64()
1730 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in getHiHalf64()
1771 SDLoc SL(Op); in SplitVectorLoad() local
1779 return DAG.getMergeValues(Ops, SL); in SplitVectorLoad()
1793 std::tie(Lo, Hi) = splitVector(Op, SL, LoVT, HiVT, DAG); in SplitVectorLoad()
1799 SDValue LoLoad = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT, in SplitVectorLoad()
1802 SDValue HiPtr = DAG.getObjectPtrOffset(SL, BasePtr, TypeSize::getFixed(Size)); in SplitVectorLoad()
1804 DAG.getExtLoad(Load->getExtensionType(), SL, HiVT, Load->getChain(), in SplitVectorLoad()
1811 Join = DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad); in SplitVectorLoad()
1813 Join = DAG.getNode(ISD::INSERT_SUBVECTOR, SL, VT, DAG.getUNDEF(VT), LoLoad, in SplitVectorLoad()
1814 DAG.getVectorIdxConstant(0, SL)); in SplitVectorLoad()
1816 HiVT.isVector() ? ISD::INSERT_SUBVECTOR : ISD::INSERT_VECTOR_ELT, SL, in SplitVectorLoad()
1818 DAG.getVectorIdxConstant(LoVT.getVectorNumElements(), SL)); in SplitVectorLoad()
1821 SDValue Ops[] = {Join, DAG.getNode(ISD::TokenFactor, SL, MVT::Other, in SplitVectorLoad()
1824 return DAG.getMergeValues(Ops, SL); in SplitVectorLoad()
1833 SDLoc SL(Op); in WidenOrSplitVectorLoad() local
1852 Load->getExtensionType(), SL, WideVT, Load->getChain(), BasePtr, SrcValue, in WidenOrSplitVectorLoad()
1855 {DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, VT, WideLoad, in WidenOrSplitVectorLoad()
1856 DAG.getVectorIdxConstant(0, SL)), in WidenOrSplitVectorLoad()
1858 SL); in WidenOrSplitVectorLoad()
1875 SDLoc SL(Op); in SplitVectorStore() local
1883 std::tie(Lo, Hi) = splitVector(Val, SL, LoVT, HiVT, DAG); in SplitVectorStore()
1885 SDValue HiPtr = DAG.getObjectPtrOffset(SL, BasePtr, LoMemVT.getStoreSize()); in SplitVectorStore()
1893 DAG.getTruncStore(Chain, SL, Lo, BasePtr, SrcValue, LoMemVT, BaseAlign, in SplitVectorStore()
1896 DAG.getTruncStore(Chain, SL, Hi, HiPtr, SrcValue.getWithOffset(Size), in SplitVectorStore()
1899 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore); in SplitVectorStore()
2351 SDLoc SL(Op); in LowerFREM() local
2357 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y, Flags); in LowerFREM()
2358 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, VT, Div, Flags); in LowerFREM()
2359 SDValue Neg = DAG.getNode(ISD::FNEG, SL, VT, Trunc, Flags); in LowerFREM()
2361 return DAG.getNode(ISD::FMA, SL, VT, Neg, Y, X, Flags); in LowerFREM()
2365 SDLoc SL(Op); in LowerFCEIL() local
2372 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFCEIL()
2374 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64); in LowerFCEIL()
2375 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64); in LowerFCEIL()
2380 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT); in LowerFCEIL()
2381 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE); in LowerFCEIL()
2382 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc); in LowerFCEIL()
2384 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero); in LowerFCEIL()
2386 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFCEIL()
2389 static SDValue extractF64Exponent(SDValue Hi, const SDLoc &SL, in extractF64Exponent() argument
2394 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32, in extractF64Exponent()
2396 DAG.getConstant(FractBits - 32, SL, MVT::i32), in extractF64Exponent()
2397 DAG.getConstant(ExpBits, SL, MVT::i32)); in extractF64Exponent()
2398 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart, in extractF64Exponent()
2399 DAG.getConstant(1023, SL, MVT::i32)); in extractF64Exponent()
2405 SDLoc SL(Op); in LowerFTRUNC() local
2410 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in LowerFTRUNC()
2416 SDValue Exp = extractF64Exponent(Hi, SL, DAG); in LowerFTRUNC()
2421 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, SL, MVT::i32); in LowerFTRUNC()
2422 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask); in LowerFTRUNC()
2425 SDValue SignBit64 = DAG.getBuildVector(MVT::v2i32, SL, {Zero, SignBit}); in LowerFTRUNC()
2426 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64); in LowerFTRUNC()
2428 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src); in LowerFTRUNC()
2430 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, SL, MVT::i64); in LowerFTRUNC()
2432 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp); in LowerFTRUNC()
2433 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64); in LowerFTRUNC()
2434 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not); in LowerFTRUNC()
2439 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, SL, MVT::i32); in LowerFTRUNC()
2441 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT); in LowerFTRUNC()
2442 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT); in LowerFTRUNC()
2444 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0); in LowerFTRUNC()
2445 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1); in LowerFTRUNC()
2447 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2); in LowerFTRUNC()
2452 SDLoc SL(Op); in LowerFROUNDEVEN() local
2458 SDValue C1 = DAG.getConstantFP(C1Val, SL, MVT::f64); in LowerFROUNDEVEN()
2459 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src); in LowerFROUNDEVEN()
2463 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign); in LowerFROUNDEVEN()
2464 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign); in LowerFROUNDEVEN()
2466 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src); in LowerFROUNDEVEN()
2469 SDValue C2 = DAG.getConstantFP(C2Val, SL, MVT::f64); in LowerFROUNDEVEN()
2473 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT); in LowerFROUNDEVEN()
2475 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2); in LowerFROUNDEVEN()
2499 SDLoc SL(Op); in LowerFROUND() local
2503 SDValue T = DAG.getNode(ISD::FTRUNC, SL, VT, X); in LowerFROUND()
2507 SDValue Diff = DAG.getNode(ISD::FSUB, SL, VT, X, T); in LowerFROUND()
2509 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, VT, Diff); in LowerFROUND()
2511 const SDValue Zero = DAG.getConstantFP(0.0, SL, VT); in LowerFROUND()
2512 const SDValue One = DAG.getConstantFP(1.0, SL, VT); in LowerFROUND()
2517 const SDValue Half = DAG.getConstantFP(0.5, SL, VT); in LowerFROUND()
2518 SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE); in LowerFROUND()
2519 SDValue OneOrZeroFP = DAG.getNode(ISD::SELECT, SL, VT, Cmp, One, Zero); in LowerFROUND()
2521 SDValue SignedOffset = DAG.getNode(ISD::FCOPYSIGN, SL, VT, OneOrZeroFP, X); in LowerFROUND()
2522 return DAG.getNode(ISD::FADD, SL, VT, T, SignedOffset); in LowerFROUND()
2526 SDLoc SL(Op); in LowerFFLOOR() local
2533 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFFLOOR()
2535 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64); in LowerFFLOOR()
2536 const SDValue NegOne = DAG.getConstantFP(-1.0, SL, MVT::f64); in LowerFFLOOR()
2541 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT); in LowerFFLOOR()
2542 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE); in LowerFFLOOR()
2543 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc); in LowerFFLOOR()
2545 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero); in LowerFFLOOR()
2547 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFFLOOR()
2594 SDLoc SL(Src); in getIsLtSmallestNormal() local
2598 DAG.getConstantFP(APFloat::getSmallestNormalized(Semantics), SL, VT); in getIsLtSmallestNormal()
2603 SL, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT), Src, in getIsLtSmallestNormal()
2611 SDLoc SL(Src); in getIsFinite() local
2614 SDValue Inf = DAG.getConstantFP(APFloat::getInf(Semantics), SL, VT); in getIsFinite()
2616 SDValue Fabs = DAG.getNode(ISD::FABS, SL, VT, Src, Flags); in getIsFinite()
2618 SL, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT), Fabs, in getIsFinite()
2626 AMDGPUTargetLowering::getScaledLogInput(SelectionDAG &DAG, const SDLoc SL, in getScaledLogInput() argument
2634 DAG.getConstantFP(APFloat::getSmallestNormalized(Semantics), SL, VT); in getScaledLogInput()
2637 SL, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT), Src, in getScaledLogInput()
2640 SDValue Scale32 = DAG.getConstantFP(0x1.0p+32, SL, VT); in getScaledLogInput()
2641 SDValue One = DAG.getConstantFP(1.0, SL, VT); in getScaledLogInput()
2643 DAG.getNode(ISD::SELECT, SL, VT, IsLtSmallestNormal, Scale32, One, Flags); in getScaledLogInput()
2645 SDValue ScaledInput = DAG.getNode(ISD::FMUL, SL, VT, Src, ScaleFactor, Flags); in getScaledLogInput()
2656 SDLoc SL(Op); in LowerFLOG2() local
2664 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src, Flags); in LowerFLOG2()
2665 SDValue Log = DAG.getNode(AMDGPUISD::LOG, SL, MVT::f32, Ext, Flags); in LowerFLOG2()
2666 return DAG.getNode(ISD::FP_ROUND, SL, VT, Log, in LowerFLOG2()
2667 DAG.getTargetConstant(0, SL, MVT::i32), Flags); in LowerFLOG2()
2671 getScaledLogInput(DAG, SL, Src, Flags); in LowerFLOG2()
2673 return DAG.getNode(AMDGPUISD::LOG, SL, VT, Src, Flags); in LowerFLOG2()
2675 SDValue Log2 = DAG.getNode(AMDGPUISD::LOG, SL, VT, ScaledInput, Flags); in LowerFLOG2()
2677 SDValue ThirtyTwo = DAG.getConstantFP(32.0, SL, VT); in LowerFLOG2()
2678 SDValue Zero = DAG.getConstantFP(0.0, SL, VT); in LowerFLOG2()
2680 DAG.getNode(ISD::SELECT, SL, VT, IsLtSmallestNormal, ThirtyTwo, Zero); in LowerFLOG2()
2681 return DAG.getNode(ISD::FSUB, SL, VT, Log2, ResultOffset, Flags); in LowerFLOG2()
2684 static SDValue getMad(SelectionDAG &DAG, const SDLoc &SL, EVT VT, SDValue X, in getMad() argument
2686 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, X, Y, Flags); in getMad()
2687 return DAG.getNode(ISD::FADD, SL, VT, Mul, C, Flags); in getMad()
2793 SDValue AMDGPUTargetLowering::LowerFLOGUnsafe(SDValue Src, const SDLoc &SL, in LowerFLOGUnsafe() argument
2804 auto [ScaledInput, IsScaled] = getScaledLogInput(DAG, SL, Src, Flags); in LowerFLOGUnsafe()
2806 SDValue LogSrc = DAG.getNode(AMDGPUISD::LOG, SL, VT, ScaledInput, Flags); in LowerFLOGUnsafe()
2808 DAG.getConstantFP(-32.0 * Log2BaseInverted, SL, VT); in LowerFLOGUnsafe()
2810 SDValue Zero = DAG.getConstantFP(0.0f, SL, VT); in LowerFLOGUnsafe()
2812 SDValue ResultOffset = DAG.getNode(ISD::SELECT, SL, VT, IsScaled, in LowerFLOGUnsafe()
2815 SDValue Log2Inv = DAG.getConstantFP(Log2BaseInverted, SL, VT); in LowerFLOGUnsafe()
2818 return DAG.getNode(ISD::FMA, SL, VT, LogSrc, Log2Inv, ResultOffset, in LowerFLOGUnsafe()
2820 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, LogSrc, Log2Inv, Flags); in LowerFLOGUnsafe()
2821 return DAG.getNode(ISD::FADD, SL, VT, Mul, ResultOffset); in LowerFLOGUnsafe()
2825 SDValue Log2Operand = DAG.getNode(LogOp, SL, VT, Src, Flags); in LowerFLOGUnsafe()
2826 SDValue Log2BaseInvertedOperand = DAG.getConstantFP(Log2BaseInverted, SL, VT); in LowerFLOGUnsafe()
2828 return DAG.getNode(ISD::FMUL, SL, VT, Log2Operand, Log2BaseInvertedOperand, in LowerFLOGUnsafe()
2836 SDLoc SL(Op); in lowerFEXP2() local
2844 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src, Flags); in lowerFEXP2()
2845 SDValue Log = DAG.getNode(AMDGPUISD::EXP, SL, MVT::f32, Ext, Flags); in lowerFEXP2()
2846 return DAG.getNode(ISD::FP_ROUND, SL, VT, Log, in lowerFEXP2()
2847 DAG.getTargetConstant(0, SL, MVT::i32), Flags); in lowerFEXP2()
2853 return DAG.getNode(AMDGPUISD::EXP, SL, MVT::f32, Src, Flags); in lowerFEXP2()
2859 SDValue RangeCheckConst = DAG.getConstantFP(-0x1.f80000p+6f, SL, VT); in lowerFEXP2()
2864 DAG.getSetCC(SL, SetCCVT, Src, RangeCheckConst, ISD::SETOLT); in lowerFEXP2()
2866 SDValue SixtyFour = DAG.getConstantFP(0x1.0p+6f, SL, VT); in lowerFEXP2()
2867 SDValue Zero = DAG.getConstantFP(0.0, SL, VT); in lowerFEXP2()
2870 DAG.getNode(ISD::SELECT, SL, VT, NeedsScaling, SixtyFour, Zero); in lowerFEXP2()
2872 SDValue AddInput = DAG.getNode(ISD::FADD, SL, VT, Src, AddOffset, Flags); in lowerFEXP2()
2873 SDValue Exp2 = DAG.getNode(AMDGPUISD::EXP, SL, VT, AddInput, Flags); in lowerFEXP2()
2875 SDValue TwoExpNeg64 = DAG.getConstantFP(0x1.0p-64f, SL, VT); in lowerFEXP2()
2876 SDValue One = DAG.getConstantFP(1.0, SL, VT); in lowerFEXP2()
2878 DAG.getNode(ISD::SELECT, SL, VT, NeedsScaling, TwoExpNeg64, One); in lowerFEXP2()
2880 return DAG.getNode(ISD::FMUL, SL, VT, Exp2, ResultScale, Flags); in lowerFEXP2()
2883 SDValue AMDGPUTargetLowering::lowerFEXPUnsafe(SDValue X, const SDLoc &SL, in lowerFEXPUnsafe() argument
2887 const SDValue Log2E = DAG.getConstantFP(numbers::log2e, SL, VT); in lowerFEXPUnsafe()
2891 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, X, Log2E, Flags); in lowerFEXPUnsafe()
2894 SL, VT, Mul, Flags); in lowerFEXPUnsafe()
2899 SDValue Threshold = DAG.getConstantFP(-0x1.5d58a0p+6f, SL, VT); in lowerFEXPUnsafe()
2900 SDValue NeedsScaling = DAG.getSetCC(SL, SetCCVT, X, Threshold, ISD::SETOLT); in lowerFEXPUnsafe()
2902 SDValue ScaleOffset = DAG.getConstantFP(0x1.0p+6f, SL, VT); in lowerFEXPUnsafe()
2904 SDValue ScaledX = DAG.getNode(ISD::FADD, SL, VT, X, ScaleOffset, Flags); in lowerFEXPUnsafe()
2907 DAG.getNode(ISD::SELECT, SL, VT, NeedsScaling, ScaledX, X); in lowerFEXPUnsafe()
2909 SDValue ExpInput = DAG.getNode(ISD::FMUL, SL, VT, AdjustedX, Log2E, Flags); in lowerFEXPUnsafe()
2911 SDValue Exp2 = DAG.getNode(AMDGPUISD::EXP, SL, VT, ExpInput, Flags); in lowerFEXPUnsafe()
2913 SDValue ResultScaleFactor = DAG.getConstantFP(0x1.969d48p-93f, SL, VT); in lowerFEXPUnsafe()
2915 DAG.getNode(ISD::FMUL, SL, VT, Exp2, ResultScaleFactor, Flags); in lowerFEXPUnsafe()
2917 return DAG.getNode(ISD::SELECT, SL, VT, NeedsScaling, AdjustedResult, Exp2, in lowerFEXPUnsafe()
2923 SDValue AMDGPUTargetLowering::lowerFEXP10Unsafe(SDValue X, const SDLoc &SL, in lowerFEXP10Unsafe() argument
2931 SDValue K0 = DAG.getConstantFP(0x1.a92000p+1f, SL, VT); in lowerFEXP10Unsafe()
2932 SDValue K1 = DAG.getConstantFP(0x1.4f0978p-11f, SL, VT); in lowerFEXP10Unsafe()
2934 SDValue Mul0 = DAG.getNode(ISD::FMUL, SL, VT, X, K0, Flags); in lowerFEXP10Unsafe()
2935 SDValue Exp2_0 = DAG.getNode(Exp2Op, SL, VT, Mul0, Flags); in lowerFEXP10Unsafe()
2936 SDValue Mul1 = DAG.getNode(ISD::FMUL, SL, VT, X, K1, Flags); in lowerFEXP10Unsafe()
2937 SDValue Exp2_1 = DAG.getNode(Exp2Op, SL, VT, Mul1, Flags); in lowerFEXP10Unsafe()
2938 return DAG.getNode(ISD::FMUL, SL, VT, Exp2_0, Exp2_1); in lowerFEXP10Unsafe()
2949 SDValue Threshold = DAG.getConstantFP(-0x1.2f7030p+5f, SL, VT); in lowerFEXP10Unsafe()
2950 SDValue NeedsScaling = DAG.getSetCC(SL, SetCCVT, X, Threshold, ISD::SETOLT); in lowerFEXP10Unsafe()
2952 SDValue ScaleOffset = DAG.getConstantFP(0x1.0p+5f, SL, VT); in lowerFEXP10Unsafe()
2953 SDValue ScaledX = DAG.getNode(ISD::FADD, SL, VT, X, ScaleOffset, Flags); in lowerFEXP10Unsafe()
2955 DAG.getNode(ISD::SELECT, SL, VT, NeedsScaling, ScaledX, X); in lowerFEXP10Unsafe()
2957 SDValue K0 = DAG.getConstantFP(0x1.a92000p+1f, SL, VT); in lowerFEXP10Unsafe()
2958 SDValue K1 = DAG.getConstantFP(0x1.4f0978p-11f, SL, VT); in lowerFEXP10Unsafe()
2960 SDValue Mul0 = DAG.getNode(ISD::FMUL, SL, VT, AdjustedX, K0, Flags); in lowerFEXP10Unsafe()
2961 SDValue Exp2_0 = DAG.getNode(Exp2Op, SL, VT, Mul0, Flags); in lowerFEXP10Unsafe()
2962 SDValue Mul1 = DAG.getNode(ISD::FMUL, SL, VT, AdjustedX, K1, Flags); in lowerFEXP10Unsafe()
2963 SDValue Exp2_1 = DAG.getNode(Exp2Op, SL, VT, Mul1, Flags); in lowerFEXP10Unsafe()
2965 SDValue MulExps = DAG.getNode(ISD::FMUL, SL, VT, Exp2_0, Exp2_1, Flags); in lowerFEXP10Unsafe()
2967 SDValue ResultScaleFactor = DAG.getConstantFP(0x1.9f623ep-107f, SL, VT); in lowerFEXP10Unsafe()
2969 DAG.getNode(ISD::FMUL, SL, VT, MulExps, ResultScaleFactor, Flags); in lowerFEXP10Unsafe()
2971 return DAG.getNode(ISD::SELECT, SL, VT, NeedsScaling, AdjustedResult, MulExps, in lowerFEXP10Unsafe()
2977 SDLoc SL(Op); in lowerFEXP() local
2985 return lowerFEXPUnsafe(X, SL, DAG, Flags); in lowerFEXP()
2994 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, X, Flags); in lowerFEXP()
2995 SDValue Lowered = lowerFEXPUnsafe(Ext, SL, DAG, Flags); in lowerFEXP()
2996 return DAG.getNode(ISD::FP_ROUND, SL, VT, Lowered, in lowerFEXP()
2997 DAG.getTargetConstant(0, SL, MVT::i32), Flags); in lowerFEXP()
3005 return IsExp10 ? lowerFEXP10Unsafe(X, SL, DAG, Flags) in lowerFEXP()
3006 : lowerFEXPUnsafe(X, SL, DAG, Flags); in lowerFEXP()
3043 SDValue C = DAG.getConstantFP(IsExp10 ? c_exp10 : c_exp, SL, VT); in lowerFEXP()
3044 SDValue CC = DAG.getConstantFP(IsExp10 ? cc_exp10 : cc_exp, SL, VT); in lowerFEXP()
3046 PH = DAG.getNode(ISD::FMUL, SL, VT, X, C, Flags); in lowerFEXP()
3047 SDValue NegPH = DAG.getNode(ISD::FNEG, SL, VT, PH, Flags); in lowerFEXP()
3048 SDValue FMA0 = DAG.getNode(ISD::FMA, SL, VT, X, C, NegPH, Flags); in lowerFEXP()
3049 PL = DAG.getNode(ISD::FMA, SL, VT, X, CC, FMA0, Flags); in lowerFEXP()
3057 SDValue CH = DAG.getConstantFP(IsExp10 ? ch_exp10 : ch_exp, SL, VT); in lowerFEXP()
3058 SDValue CL = DAG.getConstantFP(IsExp10 ? cl_exp10 : cl_exp, SL, VT); in lowerFEXP()
3060 SDValue XAsInt = DAG.getNode(ISD::BITCAST, SL, MVT::i32, X); in lowerFEXP()
3061 SDValue MaskConst = DAG.getConstant(0xfffff000, SL, MVT::i32); in lowerFEXP()
3062 SDValue XHAsInt = DAG.getNode(ISD::AND, SL, MVT::i32, XAsInt, MaskConst); in lowerFEXP()
3063 SDValue XH = DAG.getNode(ISD::BITCAST, SL, VT, XHAsInt); in lowerFEXP()
3064 SDValue XL = DAG.getNode(ISD::FSUB, SL, VT, X, XH, Flags); in lowerFEXP()
3066 PH = DAG.getNode(ISD::FMUL, SL, VT, XH, CH, Flags); in lowerFEXP()
3068 SDValue XLCL = DAG.getNode(ISD::FMUL, SL, VT, XL, CL, Flags); in lowerFEXP()
3069 SDValue Mad0 = getMad(DAG, SL, VT, XL, CH, XLCL, Flags); in lowerFEXP()
3070 PL = getMad(DAG, SL, VT, XH, CL, Mad0, Flags); in lowerFEXP()
3073 SDValue E = DAG.getNode(ISD::FROUNDEVEN, SL, VT, PH, Flags); in lowerFEXP()
3076 SDValue PHSubE = DAG.getNode(ISD::FSUB, SL, VT, PH, E, FlagsNoContract); in lowerFEXP()
3078 SDValue A = DAG.getNode(ISD::FADD, SL, VT, PHSubE, PL, Flags); in lowerFEXP()
3079 SDValue IntE = DAG.getNode(ISD::FP_TO_SINT, SL, MVT::i32, E); in lowerFEXP()
3080 SDValue Exp2 = DAG.getNode(AMDGPUISD::EXP, SL, VT, A, Flags); in lowerFEXP()
3082 SDValue R = DAG.getNode(ISD::FLDEXP, SL, VT, Exp2, IntE, Flags); in lowerFEXP()
3085 DAG.getConstantFP(IsExp10 ? -0x1.66d3e8p+5f : -0x1.9d1da0p+6f, SL, VT); in lowerFEXP()
3088 SDValue Zero = DAG.getConstantFP(0.0, SL, VT); in lowerFEXP()
3090 DAG.getSetCC(SL, SetCCVT, X, UnderflowCheckConst, ISD::SETOLT); in lowerFEXP()
3092 R = DAG.getNode(ISD::SELECT, SL, VT, Underflow, Zero, R); in lowerFEXP()
3097 DAG.getConstantFP(IsExp10 ? 0x1.344136p+5f : 0x1.62e430p+6f, SL, VT); in lowerFEXP()
3099 DAG.getSetCC(SL, SetCCVT, X, OverflowCheckConst, ISD::SETOGT); in lowerFEXP()
3101 DAG.getConstantFP(APFloat::getInf(APFloat::IEEEsingle()), SL, VT); in lowerFEXP()
3102 R = DAG.getNode(ISD::SELECT, SL, VT, Overflow, Inf, R); in lowerFEXP()
3118 auto SL = SDLoc(Op); in lowerCTLZResults() local
3130 SDValue NumExtBits = DAG.getConstant(32u - NumBits, SL, MVT::i32); in lowerCTLZResults()
3134 NewOp = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, Arg); in lowerCTLZResults()
3135 NewOp = DAG.getNode(ISD::SHL, SL, MVT::i32, NewOp, NumExtBits); in lowerCTLZResults()
3136 NewOp = DAG.getNode(Opc, SL, MVT::i32, NewOp); in lowerCTLZResults()
3138 NewOp = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Arg); in lowerCTLZResults()
3139 NewOp = DAG.getNode(Opc, SL, MVT::i32, NewOp); in lowerCTLZResults()
3140 NewOp = DAG.getNode(ISD::SUB, SL, MVT::i32, NewOp, NumExtBits); in lowerCTLZResults()
3143 return DAG.getNode(ISD::TRUNCATE, SL, ResultVT, NewOp); in lowerCTLZResults()
3147 SDLoc SL(Op); in LowerCTLZ_CTTZ() local
3169 SDValue NewOpr = DAG.getNode(NewOpc, SL, MVT::i32, Src); in LowerCTLZ_CTTZ()
3172 Op.getValueType().getScalarSizeInBits(), SL, MVT::i32); in LowerCTLZ_CTTZ()
3173 NewOpr = DAG.getNode(ISD::UMIN, SL, MVT::i32, NewOpr, ConstVal); in LowerCTLZ_CTTZ()
3175 return DAG.getNode(ISD::ZERO_EXTEND, SL, Src.getValueType(), NewOpr); in LowerCTLZ_CTTZ()
3181 SDValue OprLo = DAG.getNode(NewOpc, SL, MVT::i32, Lo); in LowerCTLZ_CTTZ()
3182 SDValue OprHi = DAG.getNode(NewOpc, SL, MVT::i32, Hi); in LowerCTLZ_CTTZ()
3190 const SDValue Const32 = DAG.getConstant(32, SL, MVT::i32); in LowerCTLZ_CTTZ()
3192 OprLo = DAG.getNode(AddOpc, SL, MVT::i32, OprLo, Const32); in LowerCTLZ_CTTZ()
3194 OprHi = DAG.getNode(AddOpc, SL, MVT::i32, OprHi, Const32); in LowerCTLZ_CTTZ()
3197 NewOpr = DAG.getNode(ISD::UMIN, SL, MVT::i32, OprLo, OprHi); in LowerCTLZ_CTTZ()
3199 const SDValue Const64 = DAG.getConstant(64, SL, MVT::i32); in LowerCTLZ_CTTZ()
3200 NewOpr = DAG.getNode(ISD::UMIN, SL, MVT::i32, NewOpr, Const64); in LowerCTLZ_CTTZ()
3203 return DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i64, NewOpr); in LowerCTLZ_CTTZ()
3234 SDLoc SL(Op); in LowerINT_TO_FP32() local
3264 ISD::SRA, SL, MVT::i32, DAG.getNode(ISD::XOR, SL, MVT::i32, Lo, Hi), in LowerINT_TO_FP32()
3265 DAG.getConstant(31, SL, MVT::i32)); in LowerINT_TO_FP32()
3267 DAG.getNode(ISD::ADD, SL, MVT::i32, DAG.getConstant(32, SL, MVT::i32), in LowerINT_TO_FP32()
3270 ShAmt = DAG.getNode(AMDGPUISD::FFBH_I32, SL, MVT::i32, Hi); in LowerINT_TO_FP32()
3273 ShAmt = DAG.getNode(ISD::SUB, SL, MVT::i32, ShAmt, in LowerINT_TO_FP32()
3274 DAG.getConstant(1, SL, MVT::i32)); in LowerINT_TO_FP32()
3275 ShAmt = DAG.getNode(ISD::UMIN, SL, MVT::i32, ShAmt, MaxShAmt); in LowerINT_TO_FP32()
3280 Sign = DAG.getNode(ISD::SRA, SL, MVT::i64, Src, in LowerINT_TO_FP32()
3281 DAG.getConstant(63, SL, MVT::i64)); in LowerINT_TO_FP32()
3283 DAG.getNode(ISD::XOR, SL, MVT::i64, in LowerINT_TO_FP32()
3284 DAG.getNode(ISD::ADD, SL, MVT::i64, Src, Sign), Sign); in LowerINT_TO_FP32()
3288 ShAmt = DAG.getNode(ISD::CTLZ, SL, MVT::i32, Hi); in LowerINT_TO_FP32()
3292 SDValue Norm = DAG.getNode(ISD::SHL, SL, MVT::i64, Src, ShAmt); in LowerINT_TO_FP32()
3297 SDValue Adjust = DAG.getNode(ISD::UMIN, SL, MVT::i32, in LowerINT_TO_FP32()
3298 DAG.getConstant(1, SL, MVT::i32), Lo); in LowerINT_TO_FP32()
3300 Norm = DAG.getNode(ISD::OR, SL, MVT::i32, Hi, Adjust); in LowerINT_TO_FP32()
3304 SDValue FVal = DAG.getNode(Opc, SL, MVT::f32, Norm); in LowerINT_TO_FP32()
3308 ShAmt = DAG.getNode(ISD::SUB, SL, MVT::i32, DAG.getConstant(32, SL, MVT::i32), in LowerINT_TO_FP32()
3312 return DAG.getNode(ISD::FLDEXP, SL, MVT::f32, FVal, ShAmt); in LowerINT_TO_FP32()
3317 SDValue Exp = DAG.getNode(ISD::SHL, SL, MVT::i32, ShAmt, in LowerINT_TO_FP32()
3318 DAG.getConstant(23, SL, MVT::i32)); in LowerINT_TO_FP32()
3320 DAG.getNode(ISD::ADD, SL, MVT::i32, in LowerINT_TO_FP32()
3321 DAG.getNode(ISD::BITCAST, SL, MVT::i32, FVal), Exp); in LowerINT_TO_FP32()
3324 Sign = DAG.getNode(ISD::SHL, SL, MVT::i32, in LowerINT_TO_FP32()
3325 DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, Sign), in LowerINT_TO_FP32()
3326 DAG.getConstant(31, SL, MVT::i32)); in LowerINT_TO_FP32()
3327 IVal = DAG.getNode(ISD::OR, SL, MVT::i32, IVal, Sign); in LowerINT_TO_FP32()
3329 return DAG.getNode(ISD::BITCAST, SL, MVT::f32, IVal); in LowerINT_TO_FP32()
3334 SDLoc SL(Op); in LowerINT_TO_FP64() local
3341 SL, MVT::f64, Hi); in LowerINT_TO_FP64()
3343 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo); in LowerINT_TO_FP64()
3345 SDValue LdExp = DAG.getNode(ISD::FLDEXP, SL, MVT::f64, CvtHi, in LowerINT_TO_FP64()
3346 DAG.getConstant(32, SL, MVT::i32)); in LowerINT_TO_FP64()
3348 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo); in LowerINT_TO_FP64()
3369 SDLoc SL(Op); in LowerUINT_TO_FP() local
3370 SDValue ToF32 = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f32, Src); in LowerUINT_TO_FP()
3371 SDValue FPRoundFlag = DAG.getIntPtrConstant(0, SL, /*isTarget=*/true); in LowerUINT_TO_FP()
3372 return DAG.getNode(ISD::FP_ROUND, SL, MVT::bf16, ToF32, FPRoundFlag); in LowerUINT_TO_FP()
3415 SDLoc SL(Op); in LowerSINT_TO_FP() local
3416 SDValue ToF32 = DAG.getNode(ISD::SINT_TO_FP, SL, MVT::f32, Src); in LowerSINT_TO_FP()
3417 SDValue FPRoundFlag = DAG.getIntPtrConstant(0, SL, /*isTarget=*/true); in LowerSINT_TO_FP()
3418 return DAG.getNode(ISD::FP_ROUND, SL, MVT::bf16, ToF32, FPRoundFlag); in LowerSINT_TO_FP()
3448 SDLoc SL(Op); in LowerFP_TO_INT64() local
3464 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, SrcVT, Src); in LowerFP_TO_INT64()
3472 Sign = DAG.getNode(ISD::SRA, SL, MVT::i32, in LowerFP_TO_INT64()
3473 DAG.getNode(ISD::BITCAST, SL, MVT::i32, Trunc), in LowerFP_TO_INT64()
3474 DAG.getConstant(31, SL, MVT::i32)); in LowerFP_TO_INT64()
3475 Trunc = DAG.getNode(ISD::FABS, SL, SrcVT, Trunc); in LowerFP_TO_INT64()
3481 llvm::bit_cast<double>(UINT64_C(/*2^-32*/ 0x3df0000000000000)), SL, in LowerFP_TO_INT64()
3484 llvm::bit_cast<double>(UINT64_C(/*-2^32*/ 0xc1f0000000000000)), SL, in LowerFP_TO_INT64()
3488 llvm::bit_cast<float>(UINT32_C(/*2^-32*/ 0x2f800000)), SL, SrcVT); in LowerFP_TO_INT64()
3490 llvm::bit_cast<float>(UINT32_C(/*-2^32*/ 0xcf800000)), SL, SrcVT); in LowerFP_TO_INT64()
3493 SDValue Mul = DAG.getNode(ISD::FMUL, SL, SrcVT, Trunc, K0); in LowerFP_TO_INT64()
3495 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, SrcVT, Mul); in LowerFP_TO_INT64()
3497 SDValue Fma = DAG.getNode(ISD::FMA, SL, SrcVT, FloorMul, K1, Trunc); in LowerFP_TO_INT64()
3501 SL, MVT::i32, FloorMul); in LowerFP_TO_INT64()
3502 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma); in LowerFP_TO_INT64()
3504 SDValue Result = DAG.getNode(ISD::BITCAST, SL, MVT::i64, in LowerFP_TO_INT64()
3505 DAG.getBuildVector(MVT::v2i32, SL, {Lo, Hi})); in LowerFP_TO_INT64()
3510 Sign = DAG.getNode(ISD::BITCAST, SL, MVT::i64, in LowerFP_TO_INT64()
3511 DAG.getBuildVector(MVT::v2i32, SL, {Sign, Sign})); in LowerFP_TO_INT64()
3514 DAG.getNode(ISD::SUB, SL, MVT::i64, in LowerFP_TO_INT64()
3515 DAG.getNode(ISD::XOR, SL, MVT::i64, Result, Sign), Sign); in LowerFP_TO_INT64()
3806 SDLoc SL(N); in performLoadCombine() local
3840 = DAG.getLoad(NewVT, SL, LN->getChain(), in performLoadCombine()
3843 SDValue BC = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad); in performLoadCombine()
3862 SDLoc SL(N); in performStoreCombine() local
3894 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NewVT, Val); in performStoreCombine()
3896 SDValue CastBack = DAG.getNode(ISD::BITCAST, SL, VT, CastVal); in performStoreCombine()
3900 return DAG.getStore(SN->getChain(), SL, CastVal, in performStoreCombine()
3917 SDLoc SL(N); in performAssertSZExtCombine() local
3922 SDValue NewInReg = DAG.getNode(N->getOpcode(), SL, SrcVT, Src, N1); in performAssertSZExtCombine()
3923 return DAG.getNode(ISD::TRUNCATE, SL, N->getValueType(0), NewInReg); in performAssertSZExtCombine()
3967 DAGCombinerInfo &DCI, const SDLoc &SL, in splitBinaryBitConstantOpImpl() argument
3974 SDValue LoRHS = DAG.getConstant(ValLo, SL, MVT::i32); in splitBinaryBitConstantOpImpl()
3975 SDValue HiRHS = DAG.getConstant(ValHi, SL, MVT::i32); in splitBinaryBitConstantOpImpl()
3977 SDValue LoAnd = DAG.getNode(Opc, SL, MVT::i32, Lo, LoRHS); in splitBinaryBitConstantOpImpl()
3978 SDValue HiAnd = DAG.getNode(Opc, SL, MVT::i32, Hi, HiRHS); in splitBinaryBitConstantOpImpl()
3985 SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {LoAnd, HiAnd}); in splitBinaryBitConstantOpImpl()
3986 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec); in splitBinaryBitConstantOpImpl()
4002 SDLoc SL(N); in performShlCombine() local
4017 SDValue Vec = DAG.getBuildVector(MVT::v2i16, SL, in performShlCombine()
4018 { DAG.getConstant(0, SL, MVT::i16), LHS->getOperand(0) }); in performShlCombine()
4019 return DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec); in performShlCombine()
4030 SDValue Shl = DAG.getNode(ISD::SHL, SL, XVT, X, SDValue(RHS, 0)); in performShlCombine()
4031 return DAG.getZExtOrTrunc(Shl, SL, VT); in performShlCombine()
4046 SDValue ShiftAmt = DAG.getConstant(RHSVal - 32, SL, MVT::i32); in performShlCombine()
4048 SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS); in performShlCombine()
4049 SDValue NewShift = DAG.getNode(ISD::SHL, SL, MVT::i32, Lo, ShiftAmt); in performShlCombine()
4051 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in performShlCombine()
4053 SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {Zero, NewShift}); in performShlCombine()
4054 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec); in performShlCombine()
4067 SDLoc SL(N); in performSraCombine() local
4073 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, in performSraCombine()
4074 DAG.getConstant(31, SL, MVT::i32)); in performSraCombine()
4076 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {Hi, NewShift}); in performSraCombine()
4077 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec); in performSraCombine()
4083 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, in performSraCombine()
4084 DAG.getConstant(31, SL, MVT::i32)); in performSraCombine()
4085 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, NewShift}); in performSraCombine()
4086 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec); in performSraCombine()
4102 SDLoc SL(N); in performSrlCombine() local
4112 ISD::AND, SL, VT, in performSrlCombine()
4113 DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(0), N->getOperand(1)), in performSrlCombine()
4114 DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(1), N->getOperand(1))); in performSrlCombine()
4128 SDValue Zero = DAG.getConstant(0, SL, MVT::i32); in performSrlCombine()
4132 SDValue NewConst = DAG.getConstant(ShiftAmt - 32, SL, MVT::i32); in performSrlCombine()
4133 SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst); in performSrlCombine()
4135 SDValue BuildPair = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, Zero}); in performSrlCombine()
4137 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildPair); in performSrlCombine()
4142 SDLoc SL(N); in performTruncateCombine() local
4155 Elt0 = DAG.getNode(ISD::BITCAST, SL, in performTruncateCombine()
4159 return DAG.getNode(ISD::TRUNCATE, SL, VT, Elt0); in performTruncateCombine()
4176 SrcElt = DAG.getNode(ISD::BITCAST, SL, in performTruncateCombine()
4180 return DAG.getNode(ISD::TRUNCATE, SL, VT, SrcElt); in performTruncateCombine()
4211 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MidVT, in performTruncateCombine()
4216 Amt = DAG.getZExtOrTrunc(Amt, SL, NewShiftVT); in performTruncateCombine()
4220 SDValue ShrunkShift = DAG.getNode(Src.getOpcode(), SL, MidVT, in performTruncateCombine()
4222 return DAG.getNode(ISD::TRUNCATE, SL, VT, ShrunkShift); in performTruncateCombine()
4234 static SDValue getMul24(SelectionDAG &DAG, const SDLoc &SL, in getMul24() argument
4238 return DAG.getNode(MulOpc, SL, MVT::i32, N0, N1); in getMul24()
4244 SDValue MulLo = DAG.getNode(MulLoOpc, SL, MVT::i32, N0, N1); in getMul24()
4245 SDValue MulHi = DAG.getNode(MulHiOpc, SL, MVT::i32, N0, N1); in getMul24()
4247 return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64, MulLo, MulHi); in getMul24()
4486 SDValue AMDGPUTargetLowering::performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, in performCtlz_CttzCombine() argument
4503 return getFFBX_U32(DAG, CmpLHS, SL, Opc); in performCtlz_CttzCombine()
4514 return getFFBX_U32(DAG, CmpLHS, SL, Opc); in performCtlz_CttzCombine()
4522 const SDLoc &SL, in distributeOpThroughSelect() argument
4529 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT, Cond, in distributeOpThroughSelect()
4532 return DAG.getNode(Op, SL, VT, NewSelect); in distributeOpThroughSelect()
4570 SDLoc SL(N); in foldFreeOpFromSelect() local
4605 NewRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in foldFreeOpFromSelect()
4610 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT, in foldFreeOpFromSelect()
4613 return DAG.getNode(LHS.getOpcode(), SL, VT, NewSelect); in foldFreeOpFromSelect()
4645 SDLoc SL(N); in performSelectCombine() local
4649 SDValue NewCond = DAG.getSetCC(SL, Cond.getValueType(), LHS, RHS, NewCC); in performSelectCombine()
4650 return DAG.getNode(ISD::SELECT, SL, VT, NewCond, False, True); in performSelectCombine()
4756 SDLoc SL(N); in performFNegCombine() local
4767 LHS = DAG.getNode(ISD::FNEG, SL, VT, LHS); in performFNegCombine()
4772 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine()
4776 SDValue Res = DAG.getNode(ISD::FADD, SL, VT, LHS, RHS, N0->getFlags()); in performFNegCombine()
4780 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
4795 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine()
4797 SDValue Res = DAG.getNode(Opc, SL, VT, LHS, RHS, N0->getFlags()); in performFNegCombine()
4801 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
4820 MHS = DAG.getNode(ISD::FNEG, SL, VT, MHS); in performFNegCombine()
4823 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine()
4827 SDValue Res = DAG.getNode(Opc, SL, VT, LHS, MHS, RHS); in performFNegCombine()
4831 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
4855 SDValue NegLHS = DAG.getNode(ISD::FNEG, SL, VT, LHS); in performFNegCombine()
4856 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine()
4859 SDValue Res = DAG.getNode(Opposite, SL, VT, NegLHS, NegRHS, N0->getFlags()); in performFNegCombine()
4863 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
4869 Ops[I] = DAG.getNode(ISD::FNEG, SL, VT, N0->getOperand(I), N0->getFlags()); in performFNegCombine()
4871 SDValue Res = DAG.getNode(AMDGPUISD::FMED3, SL, VT, Ops, N0->getFlags()); in performFNegCombine()
4876 SDValue Neg = DAG.getNode(ISD::FNEG, SL, VT, Res); in performFNegCombine()
4900 return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0)); in performFNegCombine()
4908 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
4909 return DAG.getNode(Opc, SL, VT, Neg, N0->getFlags()); in performFNegCombine()
4916 return DAG.getNode(ISD::FP_ROUND, SL, VT, in performFNegCombine()
4924 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc); in performFNegCombine()
4925 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1)); in performFNegCombine()
4931 SDLoc SL(N); in performFNegCombine() local
4937 SDValue IntFNeg = DAG.getNode(ISD::XOR, SL, SrcVT, Src, in performFNegCombine()
4938 DAG.getConstant(0x8000, SL, SrcVT)); in performFNegCombine()
4939 return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFNeg); in performFNegCombine()
4947 SDLoc SL(N); in performFNegCombine() local
4964 SDValue CastHi = DAG.getNode(ISD::BITCAST, SL, MVT::f32, HighBits); in performFNegCombine()
4965 SDValue NegHi = DAG.getNode(ISD::FNEG, SL, MVT::f32, CastHi); in performFNegCombine()
4967 DAG.getNode(ISD::BITCAST, SL, HighBits.getValueType(), NegHi); in performFNegCombine()
4973 DAG.getNode(ISD::BUILD_VECTOR, SL, BCSrc.getValueType(), Ops); in performFNegCombine()
4974 SDValue Result = DAG.getNode(ISD::BITCAST, SL, VT, Build); in performFNegCombine()
4977 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Result)); in performFNegCombine()
4989 DAG.getNode(ISD::BITCAST, SL, MVT::f32, BCSrc.getOperand(1)); in performFNegCombine()
4991 DAG.getNode(ISD::BITCAST, SL, MVT::f32, BCSrc.getOperand(2)); in performFNegCombine()
4993 SDValue NegLHS = DAG.getNode(ISD::FNEG, SL, MVT::f32, LHS); in performFNegCombine()
4994 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, MVT::f32, RHS); in performFNegCombine()
4996 return DAG.getNode(ISD::SELECT, SL, MVT::f32, BCSrc.getOperand(0), NegLHS, in performFNegCombine()
5018 SDLoc SL(N); in performFAbsCombine() local
5023 SDValue IntFAbs = DAG.getNode(ISD::AND, SL, SrcVT, Src, in performFAbsCombine()
5024 DAG.getConstant(0x7fff, SL, SrcVT)); in performFAbsCombine()
5025 return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFAbs); in performFAbsCombine()
5072 SDLoc SL(N); in PerformDAGCombine() local
5078 return DAG.getBuildVector(DestVT, SL, CastedElts); in PerformDAGCombine()
5092 SDLoc SL(N); in PerformDAGCombine() local
5094 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, in PerformDAGCombine()
5095 DAG.getConstant(Lo_32(CVal), SL, MVT::i32), in PerformDAGCombine()
5096 DAG.getConstant(Hi_32(CVal), SL, MVT::i32)); in PerformDAGCombine()
5097 return DAG.getNode(ISD::BITCAST, SL, DestVT, BV); in PerformDAGCombine()
5102 SDLoc SL(N); in PerformDAGCombine() local
5104 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, in PerformDAGCombine()
5105 DAG.getConstant(Lo_32(CVal), SL, MVT::i32), in PerformDAGCombine()
5106 DAG.getConstant(Hi_32(CVal), SL, MVT::i32)); in PerformDAGCombine()
5108 return DAG.getNode(ISD::BITCAST, SL, DestVT, Vec); in PerformDAGCombine()
5294 const SDLoc &SL, in CreateLiveInRegister() argument
5310 return DAG.getCopyFromReg(DAG.getEntryNode(), SL, VReg, VT); in CreateLiveInRegister()
5329 const SDLoc &SL, in loadStackInputValue() argument
5338 return DAG.getLoad(VT, SL, DAG.getEntryNode(), Ptr, SrcPtrInfo, Align(4), in loadStackInputValue()
5344 const SDLoc &SL, in storeStackInputValue() argument
5352 SDValue Ptr = DAG.getConstant(Offset, SL, MVT::i32); in storeStackInputValue()
5355 DAG.getCopyFromReg(Chain, SL, Info->getStackPtrOffsetReg(), MVT::i32); in storeStackInputValue()
5356 Ptr = DAG.getNode(ISD::ADD, SL, MVT::i32, SP, Ptr); in storeStackInputValue()
5357 SDValue Store = DAG.getStore(Chain, SL, ArgVal, Ptr, DstInfo, Align(4), in storeStackInputValue()
5364 EVT VT, const SDLoc &SL, in loadInputValue() argument
5369 CreateLiveInRegister(DAG, RC, Arg.getRegister(), VT, SL) : in loadInputValue()
5370 loadStackInputValue(DAG, VT, SL, Arg.getStackOffset()); in loadInputValue()
5377 V = DAG.getNode(ISD::SRL, SL, VT, V, in loadInputValue()
5378 DAG.getShiftAmountConstant(Shift, VT, SL)); in loadInputValue()
5379 return DAG.getNode(ISD::AND, SL, VT, V, in loadInputValue()
5380 DAG.getConstant(Mask >> Shift, SL, VT)); in loadInputValue()