Lines Matching refs:getOffsetReg
126 unsigned getOffsetReg() const { in getOffsetReg() function in __anon53fc71c20111::AArch64FastISel::Address
725 if (Addr.getOffsetReg()) in computeAddress()
798 if (Addr.getOffsetReg()) in computeAddress()
859 if (Addr.getOffsetReg()) in computeAddress()
889 if (!Addr.getReg() || Addr.getOffsetReg()) in computeAddress()
926 if (!Addr.getOffsetReg()) { in computeAddress()
1053 if (!ImmediateOffsetNeedsLowering && Addr.getOffset() && Addr.getOffsetReg()) in simplifyAddress()
1057 if (Addr.isRegBase() && Addr.getOffsetReg() && !Addr.getReg()) in simplifyAddress()
1063 if ((ImmediateOffsetNeedsLowering || Addr.getOffsetReg()) && Addr.isFIBase()) in simplifyAddress()
1081 Addr.getOffsetReg(), Addr.getExtendType(), in simplifyAddress()
1085 Addr.getOffsetReg(), AArch64_AM::LSL, in simplifyAddress()
1089 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(), in simplifyAddress()
1092 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(), in simplifyAddress()
1095 ResultReg = emitLSL_ri(MVT::i64, MVT::i64, Addr.getOffsetReg(), in simplifyAddress()
1148 constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1)); in addLoadStoreOperands()
1149 if (Addr.getOffsetReg()) { in addLoadStoreOperands()
1154 MIB.addReg(Addr.getOffsetReg()); in addLoadStoreOperands()
1822 Addr.getOffsetReg(); in emitLoad()
2112 Addr.getOffsetReg(); in emitStore()