Lines Matching refs:emitAnd_ri
254 unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, uint64_t Imm);
1655 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask); in emitLogicalOp()
1700 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask); in emitLogicalOp_ri()
1742 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask); in emitLogicalOp_rs()
1747 unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg, in emitAnd_ri() function in AArch64FastISel
1870 unsigned ANDReg = emitAnd_ri(MVT::i32, ResultReg, 1); in emitLoad()
2131 unsigned ANDReg = emitAnd_ri(MVT::i32, SrcReg, 1); in emitStore()
3932 SrcReg = emitAnd_ri(MVT::i64, SrcReg, 0xffffffff); in selectRet()
4001 ResultReg = emitAnd_ri(MVT::i32, Reg32, Mask); in selectTrunc()
4023 unsigned ResultReg = emitAnd_ri(MVT::i32, SrcReg, 1); in emiti1Ext()
4097 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Mask); in emitLSL_rr()
4101 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask); in emitLSL_rr()
4199 Op0Reg = emitAnd_ri(MVT::i32, Op0Reg, Mask); in emitLSR_rr()
4200 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Mask); in emitLSR_rr()
4204 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask); in emitLSR_rr()
4316 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Mask); in emitASR_rr()
4320 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask); in emitASR_rr()