Lines Matching refs:RHSReg
208 unsigned RHSReg, bool SetFlags = false,
214 unsigned RHSReg, AArch64_AM::ShiftExtendType ShiftType,
218 unsigned RHSReg, AArch64_AM::ShiftExtendType ExtType,
243 unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
245 unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
253 unsigned RHSReg, uint64_t ShiftImm);
1235 Register RHSReg = getRegForValue(RHS); in emitAddSub() local
1236 if (!RHSReg) in emitAddSub()
1238 return emitAddSub_rx(UseAdd, RetVT, LHSReg, RHSReg, ExtendType, 0, in emitAddSub()
1254 Register RHSReg = getRegForValue(MulLHS); in emitAddSub() local
1255 if (!RHSReg) in emitAddSub()
1257 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, AArch64_AM::LSL, in emitAddSub()
1277 Register RHSReg = getRegForValue(SI->getOperand(0)); in emitAddSub() local
1278 if (!RHSReg) in emitAddSub()
1280 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, ShiftType, in emitAddSub()
1289 Register RHSReg = getRegForValue(RHS); in emitAddSub() local
1290 if (!RHSReg) in emitAddSub()
1294 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
1296 return emitAddSub_rr(UseAdd, RetVT, LHSReg, RHSReg, SetFlags, WantResult); in emitAddSub()
1300 unsigned RHSReg, bool SetFlags, in emitAddSub_rr() argument
1302 assert(LHSReg && RHSReg && "Invalid register number."); in emitAddSub_rr()
1305 RHSReg == AArch64::SP || RHSReg == AArch64::WSP) in emitAddSub_rr()
1329 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rr()
1332 .addReg(RHSReg); in emitAddSub_rr()
1382 unsigned RHSReg, in emitAddSub_rs() argument
1386 assert(LHSReg && RHSReg && "Invalid register number."); in emitAddSub_rs()
1388 RHSReg != AArch64::SP && RHSReg != AArch64::WSP); in emitAddSub_rs()
1415 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rs()
1418 .addReg(RHSReg) in emitAddSub_rs()
1424 unsigned RHSReg, in emitAddSub_rx() argument
1428 assert(LHSReg && RHSReg && "Invalid register number."); in emitAddSub_rx()
1430 RHSReg != AArch64::XZR && RHSReg != AArch64::WZR); in emitAddSub_rx()
1459 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rx()
1462 .addReg(RHSReg) in emitAddSub_rx()
1522 Register RHSReg = getRegForValue(RHS); in emitFCmp() local
1523 if (!RHSReg) in emitFCmp()
1529 .addReg(RHSReg); in emitFCmp()
1569 unsigned RHSReg, bool WantResult) { in emitSubs_rr() argument
1570 return emitAddSub_rr(/*UseAdd=*/false, RetVT, LHSReg, RHSReg, in emitSubs_rr()
1575 unsigned RHSReg, in emitSubs_rs() argument
1578 return emitAddSub_rs(/*UseAdd=*/false, RetVT, LHSReg, RHSReg, ShiftType, in emitSubs_rs()
1624 Register RHSReg = getRegForValue(MulLHS); in emitLogicalOp() local
1625 if (!RHSReg) in emitLogicalOp()
1627 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal); in emitLogicalOp()
1638 Register RHSReg = getRegForValue(SI->getOperand(0)); in emitLogicalOp() local
1639 if (!RHSReg) in emitLogicalOp()
1641 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal); in emitLogicalOp()
1647 Register RHSReg = getRegForValue(RHS); in emitLogicalOp() local
1648 if (!RHSReg) in emitLogicalOp()
1652 ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, RHSReg); in emitLogicalOp()
1706 unsigned LHSReg, unsigned RHSReg, in emitLogicalOp_rs() argument
1738 fastEmitInst_rri(Opc, RC, LHSReg, RHSReg, in emitLogicalOp_rs()
3718 Register RHSReg = getRegForValue(RHS); in fastLowerIntrinsicCall() local
3719 if (!RHSReg) in fastLowerIntrinsicCall()
3723 MulReg = emitSMULL_rr(MVT::i64, LHSReg, RHSReg); in fastLowerIntrinsicCall()
3735 MulReg = emitMul_rr(VT, LHSReg, RHSReg); in fastLowerIntrinsicCall()
3736 unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, RHSReg); in fastLowerIntrinsicCall()
3748 Register RHSReg = getRegForValue(RHS); in fastLowerIntrinsicCall() local
3749 if (!RHSReg) in fastLowerIntrinsicCall()
3753 MulReg = emitUMULL_rr(MVT::i64, LHSReg, RHSReg); in fastLowerIntrinsicCall()
3764 MulReg = emitMul_rr(VT, LHSReg, RHSReg); in fastLowerIntrinsicCall()
3765 unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, RHSReg); in fastLowerIntrinsicCall()
3832 Register RHSReg = getRegForValue(II->getArgOperand(1)); in fastLowerIntrinsicCall() local
3833 if (!LHSReg || !RHSReg) in fastLowerIntrinsicCall()
3837 fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, LHSReg, RHSReg); in fastLowerIntrinsicCall()