3692     unsigned ResultReg1 = 0, ResultReg2 = 0, MulReg = 0;  in fastLowerIntrinsicCall()  local
3723         MulReg = emitSMULL_rr(MVT::i64, LHSReg, RHSReg);  in fastLowerIntrinsicCall()
3725             fastEmitInst_extractsubreg(VT, MulReg, AArch64::sub_32);  in fastLowerIntrinsicCall()
3727         emitAddSub_rx(/*UseAdd=*/false, MVT::i64, MulReg, MulSubReg,  in fastLowerIntrinsicCall()
3730         MulReg = MulSubReg;  in fastLowerIntrinsicCall()
3735         MulReg = emitMul_rr(VT, LHSReg, RHSReg);  in fastLowerIntrinsicCall()
3737         emitSubs_rs(VT, SMULHReg, MulReg, AArch64_AM::ASR, 63,  in fastLowerIntrinsicCall()
3753         MulReg = emitUMULL_rr(MVT::i64, LHSReg, RHSReg);  in fastLowerIntrinsicCall()
3757             .addReg(MulReg)  in fastLowerIntrinsicCall()
3759         MulReg = fastEmitInst_extractsubreg(VT, MulReg, AArch64::sub_32);  in fastLowerIntrinsicCall()
3764         MulReg = emitMul_rr(VT, LHSReg, RHSReg);  in fastLowerIntrinsicCall()
3772     if (MulReg) {  in fastLowerIntrinsicCall()
3775               TII.get(TargetOpcode::COPY), ResultReg1).addReg(MulReg);  in fastLowerIntrinsicCall()