Lines Matching refs:passed

35   // Big endian vectors must be passed as if they were 1-element vectors so that
42   // In AAPCS, an SRet is passed in X8, not X0 like a normal pointer parameter.
43   // However, on windows, in some circumstances, the SRet is passed in X0 or X1
45   // passed in the alternative register (X0 or X1), not X8:
68   // A SwiftError is passed in X21.
121   // The 'nest' parameter, if any, is passed in X18.
137   // Big endian vectors must be passed as if they were 1-element vectors so that
186   // Larger floating-point/vector values are passed indirectly.
218 // address is passed in X9.
221 …// ARM64EC-specific: the InReg attribute can be used to access the x64 sp passed into entry thunks…
224   // Byval aggregates are passed by pointer
231   // The 'nest' parameter, if any, is passed in R10 (X4).
234   // A SwiftError is passed in R12 (X19).
244   // The 'CFGuardTarget' parameter, if any, is passed in RAX (R8).
247   // 128 bit vectors are passed by pointer
250   // 256 bit vectors are passed by pointer
253   // 512 bit vectors are passed by pointer
256   // Long doubles are passed by pointer
259   // The first 4 MMX vector arguments are passed in GPRs.
262   // The first 4 FP/Vector arguments are passed in XMM registers.
273   // The first 4 integer arguments are passed in integer registers.
360   // An SRet is passed in X8, not X0 like a normal pointer parameter.
370   // A SwiftError is passed in X21.
637 // 'this' and the pointer return value are both passed in X0 in these cases,