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Revision tags: titanic_53.0, titanic_51.4, titanic_52.1, titanic_51.3, titanic_52.0, titanic_50.16, titanic_51.2, titanic_50.15, titanic_51.1, titanic_51.0, titanic_50.14, titanic_50.13, titanic_50.12, titanic_50.11, titanic_50.10, titanic_50.9, titanic_50.8, titanic_50.7, titanic_50.6, titanic_50.5, titanic_50.4, titanic_50.3, titanic_50.2, titanic_50.1, titanic_50.0 |
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c0a3d87b |
| 17-Jun-2009 |
Rafael Vanoni <rafael.vanoni@sun.com> |
6847706 ::pg uses cmt class name before reading class, cmt_hint obsolete
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0e751525 |
| 26-Feb-2009 |
Eric Saxe <Eric.Saxe@Sun.COM> |
PSARC 2008/777 cpupm keyword mode extensions
PSARC 2008/663 CPU Deep Idle Keyword
6567156 bring CPU power awareness to the dispatcher
6700904 deeper C-State support required on follow-ons to Intel Pe
PSARC 2008/777 cpupm keyword mode extensions
PSARC 2008/663 CPU Deep Idle Keyword
6567156 bring CPU power awareness to the dispatcher
6700904 deeper C-State support required on follow-ons to Intel Penryn processor generation microarchitecture
6805661 cmt_root may contain duplicates on UMA systems
--HG--
rename : usr/src/uts/i86pc/io/cpudrv/cpudrv_mach.c => usr/src/uts/i86pc/io/cpudrv_mach.c
rename : usr/src/uts/i86pc/io/cpudrv/cpu_acpi.c => usr/src/uts/i86pc/os/cpupm/cpu_acpi.c
rename : usr/src/uts/i86pc/io/cpudrv/cpudrv_amd.c => usr/src/uts/i86pc/os/cpupm/cpupm_amd.c
rename : usr/src/uts/i86pc/io/cpudrv/cpudrv_intel.c => usr/src/uts/i86pc/os/cpupm/cpupm_intel.c
rename : usr/src/uts/i86pc/os/cpupm.c => usr/src/uts/i86pc/os/cpupm/cpupm_mach.c
rename : usr/src/uts/i86pc/io/cpudrv/cpudrv_throttle.c => usr/src/uts/i86pc/os/cpupm/cpupm_throttle.c
rename : usr/src/uts/i86pc/io/cpudrv/pwrnow.c => usr/src/uts/i86pc/os/cpupm/pwrnow.c
rename : usr/src/uts/i86pc/io/cpudrv/speedstep.c => usr/src/uts/i86pc/os/cpupm/speedstep.c
rename : usr/src/uts/i86pc/sys/cpupm.h => usr/src/uts/i86pc/sys/cpupm_mach.h
rename : usr/src/uts/i86pc/sys/cpudrv_throttle.h => usr/src/uts/i86pc/sys/cpupm_throttle.h
show more ...
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e853d8c3 |
| 18-Sep-2007 |
jc25722 <none@none> |
6601648 MPO changes should not have added reference to routine tsb_lgrp_affinity in common header file
6602344 Niagara1 machines think of themselves as NUMA
6602360 mdb, kstat updates needed post 653
6601648 MPO changes should not have added reference to routine tsb_lgrp_affinity in common header file
6602344 Niagara1 machines think of themselves as NUMA
6602360 mdb, kstat updates needed post 6539930
6602440 physical processor view (psrinfo -vp) not supported on N1 post 6539930
6603355 MPO for sun4v platforms causes a panic when the number of mblocks > 1 and # of lgroups <= 1
show more ...
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fb2f18f8 |
| 18-Jan-2007 |
esaxe <none@none> |
6461311 multi-level CMT scheduling optimizations
6509639 cpu0 is not in the right chip_t if its chipid is not zero
--HG--
rename : usr/src/uts/common/os/chip.c => deleted_files/usr/src/uts/common/os
6461311 multi-level CMT scheduling optimizations
6509639 cpu0 is not in the right chip_t if its chipid is not zero
--HG--
rename : usr/src/uts/common/os/chip.c => deleted_files/usr/src/uts/common/os/chip.c
rename : usr/src/uts/common/sys/chip.h => deleted_files/usr/src/uts/common/sys/chip.h
show more ...
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