History log of /titanic_51/usr/src/uts/common/os/pghw.c (Results 1 – 5 of 5)
Revision Date Author Comments
# d3c97224 17-Aug-2010 Alexander Kolbasov <Alexander.Kolbasov@Sun.COM>

PSARC 2010/309 Processor Group (PG) Kstats and Tools
6923529 Provide command for printing PG utilization
6764835 Provide command for printing processor group information
6973973 Lonely Cache PG is cr

PSARC 2010/309 Processor Group (PG) Kstats and Tools
6923529 Provide command for printing PG utilization
6764835 Provide command for printing processor group information
6973973 Lonely Cache PG is created on M3000

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# b885580b 23-Dec-2009 Alexander Kolbasov <Alexander.Kolbasov@Sun.COM>

6764832 Provide user-level processor groups observability
6831680 cputrack(1) leaves its victim with unneeded cpc context
6901343 cpc context flag updates are not always atomic
6908152 Dormant thread

6764832 Provide user-level processor groups observability
6831680 cputrack(1) leaves its victim with unneeded cpc context
6901343 cpc context flag updates are not always atomic
6908152 Dormant thread CPC context affects cpu CPC consumers

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# 0e751525 26-Feb-2009 Eric Saxe <Eric.Saxe@Sun.COM>

PSARC 2008/777 cpupm keyword mode extensions
PSARC 2008/663 CPU Deep Idle Keyword
6567156 bring CPU power awareness to the dispatcher
6700904 deeper C-State support required on follow-ons to Intel Pe

PSARC 2008/777 cpupm keyword mode extensions
PSARC 2008/663 CPU Deep Idle Keyword
6567156 bring CPU power awareness to the dispatcher
6700904 deeper C-State support required on follow-ons to Intel Penryn processor generation microarchitecture
6805661 cmt_root may contain duplicates on UMA systems

--HG--
rename : usr/src/uts/i86pc/io/cpudrv/cpudrv_mach.c => usr/src/uts/i86pc/io/cpudrv_mach.c
rename : usr/src/uts/i86pc/io/cpudrv/cpu_acpi.c => usr/src/uts/i86pc/os/cpupm/cpu_acpi.c
rename : usr/src/uts/i86pc/io/cpudrv/cpudrv_amd.c => usr/src/uts/i86pc/os/cpupm/cpupm_amd.c
rename : usr/src/uts/i86pc/io/cpudrv/cpudrv_intel.c => usr/src/uts/i86pc/os/cpupm/cpupm_intel.c
rename : usr/src/uts/i86pc/os/cpupm.c => usr/src/uts/i86pc/os/cpupm/cpupm_mach.c
rename : usr/src/uts/i86pc/io/cpudrv/cpudrv_throttle.c => usr/src/uts/i86pc/os/cpupm/cpupm_throttle.c
rename : usr/src/uts/i86pc/io/cpudrv/pwrnow.c => usr/src/uts/i86pc/os/cpupm/pwrnow.c
rename : usr/src/uts/i86pc/io/cpudrv/speedstep.c => usr/src/uts/i86pc/os/cpupm/speedstep.c
rename : usr/src/uts/i86pc/sys/cpupm.h => usr/src/uts/i86pc/sys/cpupm_mach.h
rename : usr/src/uts/i86pc/sys/cpudrv_throttle.h => usr/src/uts/i86pc/sys/cpupm_throttle.h

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# e853d8c3 18-Sep-2007 jc25722 <none@none>

6601648 MPO changes should not have added reference to routine tsb_lgrp_affinity in common header file
6602344 Niagara1 machines think of themselves as NUMA
6602360 mdb, kstat updates needed post 653

6601648 MPO changes should not have added reference to routine tsb_lgrp_affinity in common header file
6602344 Niagara1 machines think of themselves as NUMA
6602360 mdb, kstat updates needed post 6539930
6602440 physical processor view (psrinfo -vp) not supported on N1 post 6539930
6603355 MPO for sun4v platforms causes a panic when the number of mblocks > 1 and # of lgroups <= 1

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# fb2f18f8 18-Jan-2007 esaxe <none@none>

6461311 multi-level CMT scheduling optimizations
6509639 cpu0 is not in the right chip_t if its chipid is not zero

--HG--
rename : usr/src/uts/common/os/chip.c => deleted_files/usr/src/uts/common/os

6461311 multi-level CMT scheduling optimizations
6509639 cpu0 is not in the right chip_t if its chipid is not zero

--HG--
rename : usr/src/uts/common/os/chip.c => deleted_files/usr/src/uts/common/os/chip.c
rename : usr/src/uts/common/sys/chip.h => deleted_files/usr/src/uts/common/sys/chip.h

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