| 6ebff712 | 05-Jul-2025 |
Han Gao <rabenda.cn@gmail.com> |
riscv: dts: sophgo: add ziccrse for sg2042
sg2042 support Ziccrse ISA extension [1].
Link: https://lore.kernel.org/all/20241103145153.105097-12-alexghiti@rivosinc.com/ [1]
Signed-off-by: Han Gao <
riscv: dts: sophgo: add ziccrse for sg2042
sg2042 support Ziccrse ISA extension [1].
Link: https://lore.kernel.org/all/20241103145153.105097-12-alexghiti@rivosinc.com/ [1]
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Reviewed-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/859df9a05e1693fec9bd2c7dcf14415bb15230bd.1751698574.git.rabenda.cn@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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| a5fb9056 | 05-Jul-2025 |
Han Gao <rabenda.cn@gmail.com> |
riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
The sg2042 SoCs support xtheadvector [1] so it can be included in the
devicetree. Also include vlenb for the cpu. And set vlenb=16 [2].
riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
The sg2042 SoCs support xtheadvector [1] so it can be included in the
devicetree. Also include vlenb for the cpu. And set vlenb=16 [2].
This can be tested by passing the "mitigations=off" kernel parameter.
Link: https://lore.kernel.org/linux-riscv/20241113-xtheadvector-v11-4-236c22791ef9@rivosinc.com/ [1]
Link: https://lore.kernel.org/linux-riscv/aCO44SAoS2kIP61r@ghost/ [2]
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Reviewed-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/915bef0530dee6c8bc0ae473837a4bd6786fa4fb.1751698574.git.rabenda.cn@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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| 817c89a6 | 17-Jun-2025 |
Inochi Amaoto <inochiama@gmail.com> |
riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC
Add known reset configuration for existed device.
Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Link: https
riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC
Add known reset configuration for existed device.
Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Link: https://lore.kernel.org/r/20250617070144.1149926-5-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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| 02d548e5 | 13-Jun-2025 |
Inochi Amaoto <inochiama@gmail.com> |
riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property
The kernel complains no "riscv,cbop-block-size" and disables the Zicbop
extension. Add the missing property to keep it function
riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property
The kernel complains no "riscv,cbop-block-size" and disables the Zicbop
extension. Add the missing property to keep it functional.
Fixes: ae5bac370ed4 ("riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10")
Link: https://lore.kernel.org/r/20250613074513.1683624-1-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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| ff908973 | 09-Jun-2025 |
Longbin Li <looong.bin@gmail.com> |
riscv: dts: sophgo: add pwm controller for SG2044
Add pwm device node for SG2044.
Signed-off-by: Longbin Li <looong.bin@gmail.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lo
riscv: dts: sophgo: add pwm controller for SG2044
Add pwm device node for SG2044.
Signed-off-by: Longbin Li <looong.bin@gmail.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/20250608232836.784737-12-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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| 162b265c | 09-Jun-2025 |
Longbin Li <looong.bin@gmail.com> |
riscv: dts: sophgo: add SG2044 SPI NOR controller driver
Add SPI NOR device node for SG2044.
Signed-off-by: Longbin Li <looong.bin@gmail.com>
Link: https://lore.kernel.org/r/20250608232836.784737-1
riscv: dts: sophgo: add SG2044 SPI NOR controller driver
Add SPI NOR device node for SG2044.
Signed-off-by: Longbin Li <looong.bin@gmail.com>
Link: https://lore.kernel.org/r/20250608232836.784737-11-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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| c20e152a | 09-Jun-2025 |
Inochi Amaoto <inochiama@gmail.com> |
riscv: dts: sophgo: sg2044: Add pinctrl device
Add pinctrl DT node and configuration for SG2044.
Link: https://lore.kernel.org/r/20250608232836.784737-10-inochiama@gmail.com
Signed-off-by: Inochi A
riscv: dts: sophgo: sg2044: Add pinctrl device
Add pinctrl DT node and configuration for SG2044.
Link: https://lore.kernel.org/r/20250608232836.784737-10-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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| 2b09dad7 | 09-Jun-2025 |
Inochi Amaoto <inochiama@gmail.com> |
riscv: dts: sophgo: sophgo-srd3-10: add HWMON MCU device
Add MCU devicetree node for Sophgo SRD3-10 board. This is used to
provide SUSP function for the board.
Link: https://lore.kernel.org/r/20250
riscv: dts: sophgo: sophgo-srd3-10: add HWMON MCU device
Add MCU devicetree node for Sophgo SRD3-10 board. This is used to
provide SUSP function for the board.
Link: https://lore.kernel.org/r/20250608232836.784737-8-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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| f88aa1f1 | 09-Jun-2025 |
Inochi Amaoto <inochiama@gmail.com> |
riscv: dts: sophgo: sg2044: add DMA controller device
The DMA controller of SG2044 is a standard Synopsys IP, which is
already supported by the kernel.
Add DMA controller DT node for SG2044.
Link:
riscv: dts: sophgo: sg2044: add DMA controller device
The DMA controller of SG2044 is a standard Synopsys IP, which is
already supported by the kernel.
Add DMA controller DT node for SG2044.
Link: https://lore.kernel.org/r/20250608232836.784737-6-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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| 11350d2f | 09-Jun-2025 |
Inochi Amaoto <inochiama@gmail.com> |
riscv: dts: sophgo: sg2044: Add I2C device
The I2C controller of SG2044 is a standard Synopsys IP, with one
the ref clock is need.
Add I2C DT node for SG2044 SoC.
Link: https://lore.kernel.org/r/2
riscv: dts: sophgo: sg2044: Add I2C device
The I2C controller of SG2044 is a standard Synopsys IP, with one
the ref clock is need.
Add I2C DT node for SG2044 SoC.
Link: https://lore.kernel.org/r/20250608232836.784737-5-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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| cfb88696 | 09-Jun-2025 |
Inochi Amaoto <inochiama@gmail.com> |
riscv: dts: sophgo: sg2044: Add GPIO device
The GPIO controller is a standard Synopsys IP, which is already
supported by the kernel.
Add GPIO DT node for SG2044 SoC.
Link: https://lore.kernel.org/
riscv: dts: sophgo: sg2044: Add GPIO device
The GPIO controller is a standard Synopsys IP, which is already
supported by the kernel.
Add GPIO DT node for SG2044 SoC.
Link: https://lore.kernel.org/r/20250608232836.784737-4-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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| 1995b264 | 09-Jun-2025 |
Inochi Amaoto <inochiama@gmail.com> |
riscv: dts: sophgo: sg2044: Add clock controller device
Add clock controller and pll clock node for sg2044.
Link: https://lore.kernel.org/r/20250608232836.784737-3-inochiama@gmail.com
Signed-off-by
riscv: dts: sophgo: sg2044: Add clock controller device
Add clock controller and pll clock node for sg2044.
Link: https://lore.kernel.org/r/20250608232836.784737-3-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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| 95f119e3 | 09-Jun-2025 |
Inochi Amaoto <inochiama@gmail.com> |
riscv: dts: sophgo: sg2044: Add system controller device
The TOP system controller device is necessary for the SG2044 clock
controller. Add it to the SoC device tree.
Link: https://lore.kernel.org/
riscv: dts: sophgo: sg2044: Add system controller device
The TOP system controller device is necessary for the SG2044 clock
controller. Add it to the SoC device tree.
Link: https://lore.kernel.org/r/20250608232836.784737-2-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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| ae5bac37 | 14-Apr-2025 |
Inochi Amaoto <inochiama@gmail.com> |
riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10
Sophgo SG2044 SRD3-10 board bases on Sophgo SG2044 SoC.
This board includes 5 uart ports, 5 pcie x8 slots, 1 1G Ethernet port,
1 microSD
riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10
Sophgo SG2044 SRD3-10 board bases on Sophgo SG2044 SoC.
This board includes 5 uart ports, 5 pcie x8 slots, 1 1G Ethernet port,
1 microSD slot.
Add initial device tree of this board with uart support.
Link: https://lore.kernel.org/r/20250413223507.46480-11-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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| e595fa85 | 30-Apr-2025 |
Inochi Amaoto <inochiama@gmail.com> |
riscv: dts: sopgho: use SOC_PERIPHERAL_IRQ to calculate interrupt number
Since riscv and arm architecture use different interrupt definitions,
use a macro SOC_PERIPHERAL_IRQ mask this difference.
S
riscv: dts: sopgho: use SOC_PERIPHERAL_IRQ to calculate interrupt number
Since riscv and arm architecture use different interrupt definitions,
use a macro SOC_PERIPHERAL_IRQ mask this difference.
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Link: https://lore.kernel.org/r/20250430012654.235830-5-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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| a0cd6d17 | 30-Apr-2025 |
Inochi Amaoto <inochiama@gmail.com> |
riscv: dts: sophgo: rename header file cv18xx.dtsi to cv180x.dtsi
As the cv18xx.dtsi serves as a common peripheral header for all
riscv cv180x/cv181x/sg200x SoCs, it not cover the entire cv18xx
seri
riscv: dts: sophgo: rename header file cv18xx.dtsi to cv180x.dtsi
As the cv18xx.dtsi serves as a common peripheral header for all
riscv cv180x/cv181x/sg200x SoCs, it not cover the entire cv18xx
series as there is cv182x and cv183x. So rename the header file
to make it precise.
Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Link: https://lore.kernel.org/r/20250430012654.235830-4-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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| 0212bd4f | 30-Apr-2025 |
Inochi Amaoto <inochiama@gmail.com> |
riscv: dts: sophgo: Move riscv cpu definition to a separate file
As sg2000 and sg2002 can boot from an arm a53 core, it is not
suitable to left the riscv cpu definition in the common peripheral
head
riscv: dts: sophgo: Move riscv cpu definition to a separate file
As sg2000 and sg2002 can boot from an arm a53 core, it is not
suitable to left the riscv cpu definition in the common peripheral
header.
Move the riscv related device into a separate header file, so the
arm subsystem can reuse the common peripheral header.
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Link: https://lore.kernel.org/r/20250430012654.235830-3-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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| 33da812c | 30-Apr-2025 |
Inochi Amaoto <inochiama@gmail.com> |
riscv: dts: sophgo: Move all soc specific device into soc dtsi file
Although the cv1800b/cv1812h/sg2000/sg2002 share most peripherals,
some basic peripherals, like clock, pinctrl, clint and plint, a
riscv: dts: sophgo: Move all soc specific device into soc dtsi file
Although the cv1800b/cv1812h/sg2000/sg2002 share most peripherals,
some basic peripherals, like clock, pinctrl, clint and plint, are
not shared. These are caused by not only historical reason (plic,
clint), but also the fact the device is not the same (clock, pinctrl).
It is good to override device compatible when the SoC number is small,
but now it is a burden for maintenance, and it is kind of annoyed to
explain why using override. So it is time to move this out of the
common peripheral header.
Move all soc related peripheral device from common peripheral header
to the soc specific header to get rid of most compatible override.
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Link: https://lore.kernel.org/r/20250430012654.235830-2-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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