Revision tags: v6.13 |
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94467a22 |
| 14-Jan-2025 |
Linus Walleij <linus.walleij@linaro.org> |
Merge tag 'renesas-pinctrl-for-v6.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v6.14 (take two)
- Add support for alpha
Merge tag 'renesas-pinctrl-for-v6.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v6.14 (take two)
- Add support for alpha-numerical port references on the RZ/V2H SoC, - Add support for the RZ/G3E (R9A09G047) Soc.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Revision tags: v6.13-rc7, v6.13-rc6 |
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75ea9cf9 |
| 03-Jan-2025 |
Geert Uytterhoeven <geert+renesas@glider.be> |
Merge tag 'renesas-r9a09g047-dt-binding-defs-tag2' into renesas-pinctrl-for-v6.14
Renesas RZ/G3E Pin Control DT Binding Definitions
Pin control DT bindings and binding definitions for the Renesas R
Merge tag 'renesas-r9a09g047-dt-binding-defs-tag2' into renesas-pinctrl-for-v6.14
Renesas RZ/G3E Pin Control DT Binding Definitions
Pin control DT bindings and binding definitions for the Renesas RZ/G3E (R9A09G047) SoC, shared by driver and DT source files.
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Revision tags: v6.13-rc5, v6.13-rc4 |
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45b177c3 |
| 20-Dec-2024 |
Arnd Bergmann <arnd@arndb.de> |
Merge tag 'renesas-dts-for-v6.14-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.14
- Add more serial (SCIF), power monitor, AD
Merge tag 'renesas-dts-for-v6.14-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.14
- Add more serial (SCIF), power monitor, ADC, and sound support for the RZ/G3S SoC and the RZ/G3S SMARC SoM and development board, - Add support for the R-Car V4H ES3.0 (R8A779G3) SoC on the White Hawk Single development board, - Add display support for the R-Car V4M SoC and the Gray Hawk Single development board, - Add video capture support for the Gray Hawk Single development board, - Add initial support for the RZ/G3E (R9A09G047) SoC and the RZ/G3E SMARC SoM and Carrier-II EVK development board, - Add support for 5-port MATEnet on the Falcon Ethernet sub-board, - Miscellaneous fixes and improvements.
* tag 'renesas-dts-for-v6.14-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (33 commits) arm64: dts: renesas: r9a09g047: Add I2C nodes arm64: dts: renesas: rzg3s-smarc: Add sound card arm64: dts: renesas: rzg3s-smarc: Enable SSI3 arm64: dts: renesas: Add da7212 audio codec node arm64: dts: renesas: rzg3s-smarc-som: Add versa3 clock generator node arm64: dts: renesas: r9a08g045: Add SSI nodes arm64: dts: renesas: rzg3s-smarc-som: Enable ADC arm64: dts: renesas: r9a08g045: Add ADC node arm64: dts: renesas: Add initial device tree for RZ/G3E SMARC EVK board arm64: dts: renesas: Add initial support for RZ/G3E SMARC SoM arm64: dts: renesas: r9a09g047: Add OPP table arm64: dts: renesas: Add initial DTSI for RZ/G3E SoC arm64: dts: renesas: falcon-ethernet: Describe PHYs connected on the breakout board arm64: dts: renesas: r8a779a0: Remove address- and size-cells from AVB[1-5] dt-bindings: clock: renesas: Document RZ/G3E SoC CPG dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants arm64: dts: renesas: gray-hawk-single: Add video capture support arm64: dts: renesas: gray-hawk-single: Add DisplayPort support arm64: dts: renesas: r8a779h0: Add display support ...
Link: https://lore.kernel.org/r/cover.1734689803.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Revision tags: v6.13-rc3 |
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6977c89b |
| 13-Dec-2024 |
Geert Uytterhoeven <geert+renesas@glider.be> |
Merge tag 'renesas-r9a09g047-dt-binding-defs-tag1' into renesas-dts-for-v6.14
Renesas RZ/G3E DT Binding Definitions
DT bindings and binding definitions for the Renesas RZ/G3E (R9A09G047) SoC, share
Merge tag 'renesas-r9a09g047-dt-binding-defs-tag1' into renesas-dts-for-v6.14
Renesas RZ/G3E DT Binding Definitions
DT bindings and binding definitions for the Renesas RZ/G3E (R9A09G047) SoC, shared by driver and DT source files.
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641b0c64 |
| 22-Jan-2025 |
Linus Torvalds <torvalds@linux-foundation.org> |
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd: "A pretty quiet cycle this time around. We have a bunch of new Qualcomm cl
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd: "A pretty quiet cycle this time around. We have a bunch of new Qualcomm clk drivers, per usual, and then a handful of drivers for other SoCs. Then the usual pile of cleanups is fairly small data fixes or converting DT bindings to YAML so they can be validated.
No changes to the core framework besides an OF node refcount bump that never got decremented.
New Drivers:
- 5L35023 variant of Versa 3 clock generator
- Various Qualcomm clk controllers: IPQ CMN PLL, SM6115 LPASS, SM750 global, tcsr, rpmh, and display. X Plus GPU and global. QCS615 rpmh and MSM8937 and MSM8940 RPM.
- Qualcomm Pongo and Taycan Alpha PLLs
- Qualcomm IPQ5424 NoC-related interconnect clks
- Renesas RZ/G3E (R9A09G047) SoC clk driver
- SAMA7D65 SoC clk driver
- Samsung Exynos990 SoC clk driver"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (159 commits) clk: analogbits: Fix incorrect calculation of vco rate delta clk: bcm: rpi: Add disp clock clk: bcm: rpi: Create helper to retrieve private data clk: bcm: rpi: Enable minimize for all firmware clocks clk: bcm: rpi: Allow cpufreq driver to also adjust gpu clocks clk: bcm: rpi: Add ISP to exported clocks clk: stm32f4: support spread spectrum clock generation clk: stm32f4: use FIELD helpers to access the PLLCFGR fields dt-bindings: clock: st,stm32-rcc: support spread spectrum clocking dt-bindings: clock: convert stm32 rcc bindings to json-schema clk: Use str_enable_disable-like helpers clk: clk-loongson2: Fix the number count of clk provider clk: clk-loongson2: Switch to use devm_clk_hw_register_fixed_rate_parent_data() clk: starfive: Make _clk_get become a common helper function clk: en7523: Add clock for eMMC for EN7581 dt-bindings: clock: add ID for eMMC for EN7581 dt-bindings: clock: drop NUM_CLOCKS define for EN7581 clk: en7523: Rework clock handling for different clock numbers clk: thead: Fix cpu2vp_clk for TH1520 AP_SUBSYS clocks clk: thead: Add CLK_IGNORE_UNUSED to fix TH1520 boot ...
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70741cc3 |
| 21-Jan-2025 |
Stephen Boyd <sboyd@kernel.org> |
Merge branches 'clk-cleanup', 'clk-renesas', 'clk-mediatek', 'clk-samsung' and 'clk-socfpga' into clk-next
- Support for 5L35023 variant of Versa 3 clock generator
* clk-cleanup: clk: analogbits
Merge branches 'clk-cleanup', 'clk-renesas', 'clk-mediatek', 'clk-samsung' and 'clk-socfpga' into clk-next
- Support for 5L35023 variant of Versa 3 clock generator
* clk-cleanup: clk: analogbits: Fix incorrect calculation of vco rate delta clk: Use str_enable_disable-like helpers clk: clk-loongson2: Switch to use devm_clk_hw_register_fixed_rate_parent_data() clk: starfive: Make _clk_get become a common helper function clk: ep93xx: make const read-only arrays static clk: lmk04832: make read-only const arrays static clk: ti: use kcalloc() instead of kzalloc() dt-bindings: clock: st,stm32mp1-rcc: complete the reference path dt-bindings: clock: st,stm32mp1-rcc: fix reference paths dt-bindings: clock: ti: Convert composite.txt to json-schema dt-bindings: clock: ti: Convert gate.txt to json-schema clk: Drop obsolete devm_clk_bulk_get_all_enable() helper PCI: exynos: Switch to devm_clk_bulk_get_all_enabled() soc: mediatek: pwrap: Switch to devm_clk_bulk_get_all_enabled() clk: davinci: remove platform data struct clk: fix an OF node reference leak in of_clk_get_parent_name() clk: mmp: pxa1908-apbc: Fix NULL vs IS_ERR() check clk: mmp: pxa1908-apbcp: Fix a NULL vs IS_ERR() check clk: mmp: pxa1908-mpmu: Fix a NULL vs IS_ERR() check
* clk-renesas: (24 commits) dt-bindings: clock: renesas,r9a08g045-vbattb: Fix include guard clk: renesas: r9a09g057: Add clock and reset entries for GIC clk: renesas: r9a09g057: Add reset entry for SYS clk: renesas: r8a779g0: Add VSPX clocks clk: renesas: r8a779g0: Add FCPVX clocks clk: renesas: r9a09g047: Add I2C clocks/resets clk: renesas: r9a09g047: Add CA55 core clocks clk: renesas: rzv2h: Add support for RZ/G3E SoC clk: renesas: rzv2h: Add MSTOP support dt-bindings: clock: renesas: Document RZ/G3E SoC CPG dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants clk: versaclock3: Add support for the 5L35023 variant dt-bindings: clock: versaclock3: Document 5L35023 Versa3 clock generator clk: versaclock3: Prepare for the addition of 5L35023 device clk: renesas: r9a08g045: Add clocks, resets and power domain support for the ADC IP clk: renesas: r8a779h0: Add display clocks clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets clk: renesas: rzv2h: Add selective Runtime PM support for clocks clk: renesas: r9a06g032: Use BIT macro consistently ...
* clk-mediatek: clk: ralink: mtmips: remove duplicated 'xtal' clock for Ralink SoC RT3883 clk: mediatek: mt2701-img: add missing dummy clk clk: mediatek: mt2701-mm: add missing dummy clk clk: mediatek: mt2701-bdp: add missing dummy clk clk: mediatek: mt2701-aud: fix conversion to mtk_clk_simple_probe clk: mediatek: mt2701-vdec: fix conversion to mtk_clk_simple_probe
* clk-samsung: clk: samsung: Introduce Exynos990 clock controller driver clk: samsung: clk-pll: Add support for pll_{0717x, 0718x, 0732x} dt-bindings: clock: samsung: Add Exynos990 SoC CMU bindings
* clk-socfpga: clk: socfpga: arria10: Optimize local variables in clk_pll_recalc_rate()
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83f6c3de |
| 07-Jan-2025 |
Stephen Boyd <sboyd@kernel.org> |
Merge tag 'renesas-clk-for-v6.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add suppo
Merge tag 'renesas-clk-for-v6.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add support for the RZ/G3E (R9A09G047) SoC - Add Module Stop (MSTOP) support on RZ/V2H - Add Image Signal Processor helper block (FCPVX and VSPX) clocks on R-Car V4H SoC - Add System Controller (SYS) reset and Generic Interrupt Controller (GIC) clock and reset entries on RZ/V2H
* tag 'renesas-clk-for-v6.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: dt-bindings: clock: renesas,r9a08g045-vbattb: Fix include guard clk: renesas: r9a09g057: Add clock and reset entries for GIC clk: renesas: r9a09g057: Add reset entry for SYS clk: renesas: r8a779g0: Add VSPX clocks clk: renesas: r8a779g0: Add FCPVX clocks clk: renesas: r9a09g047: Add I2C clocks/resets clk: renesas: r9a09g047: Add CA55 core clocks clk: renesas: rzv2h: Add support for RZ/G3E SoC clk: renesas: rzv2h: Add MSTOP support dt-bindings: clock: renesas: Document RZ/G3E SoC CPG dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants
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6b4a095c |
| 07-Jan-2025 |
Geert Uytterhoeven <geert+renesas@glider.be> |
Merge tag 'renesas-r9a09g047-dt-binding-defs-tag1' into renesas-clk-for-v6.14
Renesas RZ/G3E DT Binding Definitions
DT bindings and binding definitions for the Renesas RZ/G3E (R9A09G047) SoC, share
Merge tag 'renesas-r9a09g047-dt-binding-defs-tag1' into renesas-clk-for-v6.14
Renesas RZ/G3E DT Binding Definitions
DT bindings and binding definitions for the Renesas RZ/G3E (R9A09G047) SoC, shared by driver and DT source files.
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Revision tags: v6.13-rc2 |
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25458fdd |
| 03-Dec-2024 |
Biju Das <biju.das.jz@bp.renesas.com> |
dt-bindings: clock: renesas: Document RZ/G3E SoC CPG
Document the device tree bindings for the Renesas RZ/G3E SoC Clock Pulse Generator (CPG).
Also define constants for the core clocks of the RZ/G3
dt-bindings: clock: renesas: Document RZ/G3E SoC CPG
Document the device tree bindings for the Renesas RZ/G3E SoC Clock Pulse Generator (CPG).
Also define constants for the core clocks of the RZ/G3E SoC.
Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241203105005.103927-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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