Merge branches 'clk-mediatek', 'clk-hisi', 'clk-allwinner', 'clk-ux500' and 'clk-renesas' into clk-next

* clk-mediatek:
clk: mediatek: add audsys support for MT2701
clk: mediatek: add devm_of_pl

Merge branches 'clk-mediatek', 'clk-hisi', 'clk-allwinner', 'clk-ux500' and 'clk-renesas' into clk-next

* clk-mediatek:
clk: mediatek: add audsys support for MT2701
clk: mediatek: add devm_of_platform_populate() for MT7622 audsys
dt-bindings: clock: mediatek: add audsys support for MT2701
dt-bindings: clock: mediatek: update audsys documentation to adapt MFD device
clk: mediatek: update missing clock data for MT7622 audsys
clk: mediatek: fix PWM clock source by adding a fixed-factor clock
dt-bindings: clock: mediatek: add binding for fixed-factor clock axisel_d4

* clk-hisi:
clk: hisilicon: fix potential NULL dereference in hisi_clk_alloc()
clk: hisilicon: mark wdt_mux_p[] as const
clk: hisilicon: Mark phase_ops static
clk: hi3798cv200: add emmc sample and drive clock
clk: hisilicon: add hisi phase clock support
clk: hi3798cv200: add COMBPHY0 clock support
clk: hi3798cv200: fix define indentation
clk: hi3798cv200: add support for HISTB_USB2_OTG_UTMI_CLK
clk: hi3798cv200: correct IR clock parent
clk: hi3798cv200: fix unregister call sequence in error path

* clk-allwinner:
clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU
clk: sunxi-ng: add support for the Allwinner H6 CCU
dt-bindings: add device tree binding for Allwinner H6 main CCU
clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks
clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO
clk: sunxi-ng: h3: h5: Allow some clocks to set parent rate
clk: sunxi-ng: h3: h5: Add minimal rate for video PLL
clk: sunxi-ng: Add check for minimal rate to NM PLLs
clk: sunxi-ng: Use u64 for calculation of nkmp rate
clk: sunxi-ng: Mask nkmp factors when setting register
clk: sunxi-ng: remove select on obsolete SUNXI_CCU_X kconfig name

* clk-ux500:
clk: ux500: Drop AB8540/9540 support

* clk-renesas: (27 commits)
clk: renesas: cpg-mssr: Adjust r8a77980 ifdef
clk: renesas: rcar-gen3: Always use readl()/writel()
clk: renesas: sh73a0: Always use readl()/writel()
clk: renesas: rza1: Always use readl()/writel()
clk: renesas: rcar-gen2: Always use readl()/writel()
clk: renesas: r8a7740: Always use readl()/writel()
clk: renesas: r8a73a4: Always use readl()/writel()
clk: renesas: mstp: Always use readl()/writel()
clk: renesas: div6: Always use readl()/writel()
clk: fix false-positive Wmaybe-uninitialized warning
clk: renesas: r8a77965: Replace DU2 clock
clk: renesas: cpg-mssr: Add support for R-Car M3-N
clk: renesas: cpg-mssr: add R8A77980 support
dt-bindings: clock: add R8A77980 CPG core clock definitions
clk: renesas: r8a7792: Add rwdt clock
clk: renesas: r8a7794: Add rwdt clock
clk: renesas: r8a7791/r8a7793: Add rwdt clock
clk: renesas: r8a7790: Add rwdt clock
clk: renesas: r8a7745: Add rwdt clock
clk: renesas: r8a7743: Add rwdt clock
...

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Merge tag 'sunxi-clk-for-4.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clock changes from Maxime Ripard:

Our usual bunch of changes for the

Merge tag 'sunxi-clk-for-4.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clock changes from Maxime Ripard:

Our usual bunch of changes for the next merge window. The most significant
addition is the support of the H6 clock unit. Other than that, there's a
bunch of fixes for the video clocks on the H3 and H5, and some Kconfig
cleanup.

* tag 'sunxi-clk-for-4.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU
clk: sunxi-ng: add support for the Allwinner H6 CCU
dt-bindings: add device tree binding for Allwinner H6 main CCU
clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks
clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO
clk: sunxi-ng: h3: h5: Allow some clocks to set parent rate
clk: sunxi-ng: h3: h5: Add minimal rate for video PLL
clk: sunxi-ng: Add check for minimal rate to NM PLLs
clk: sunxi-ng: Use u64 for calculation of nkmp rate
clk: sunxi-ng: Mask nkmp factors when setting register
clk: sunxi-ng: remove select on obsolete SUNXI_CCU_X kconfig name

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clk: sunxi-ng: add support for the Allwinner H6 CCU

The Allwinner H6 SoC has a CCU which has been largely rearranged.

Add support for it in the sunxi-ng CCU framework.

Signed-off-by: Icenowy Zheng

clk: sunxi-ng: add support for the Allwinner H6 CCU

The Allwinner H6 SoC has a CCU which has been largely rearranged.

Add support for it in the sunxi-ng CCU framework.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

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