| b16a213b | 25-Jun-2020 |
Antoine Tenart <antoine.tenart@bootlin.com> |
net: phy: mscc: fix a possible double unlock
On vsc8584_ptp_init failure we jump to the 'err' label, which unlocks
the MDIO bus lock. But vsc8584_ptp_init isn't called with the MDIO bus
lock taken,
net: phy: mscc: fix a possible double unlock
On vsc8584_ptp_init failure we jump to the 'err' label, which unlocks
the MDIO bus lock. But vsc8584_ptp_init isn't called with the MDIO bus
lock taken, which could result in a double unlock. Fix this.
Fixes: ab2bf9339357 ("net: phy: mscc: 1588 block initialization")
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| 7d272e63 | 23-Jun-2020 |
Antoine Tenart <antoine.tenart@bootlin.com> |
net: phy: mscc: timestamping and PHC support
This patch adds support for PHC and timestamping operations for the MSCC
PHY. PTP 1-step and 2-step modes are supported, over Ethernet and UDP.
To get a
net: phy: mscc: timestamping and PHC support
This patch adds support for PHC and timestamping operations for the MSCC
PHY. PTP 1-step and 2-step modes are supported, over Ethernet and UDP.
To get and set the PHC time, a GPIO has to be used and changes are only
retrieved or committed when on a rising edge. The same GPIO is shared by
all PHYs, so the granularity of the lock protecting it has to be
different from the ones protecting the 1588 registers (the VSC8584 PHY
has 2 1588 blocks, and a single load/save pin).
Co-developed-by: Quentin Schulz <quentin.schulz@bootlin.com>
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| ab2bf933 | 23-Jun-2020 |
Quentin Schulz <quentin.schulz@bootlin.com> |
net: phy: mscc: 1588 block initialization
This patch adds the first parts of the 1588 support in the MSCC PHY,
with registers definition and the 1588 block initialization.
Those PHYs are distribute
net: phy: mscc: 1588 block initialization
This patch adds the first parts of the 1588 support in the MSCC PHY,
with registers definition and the 1588 block initialization.
Those PHYs are distributed in hardware packages containing multiple
times the PHY. The VSC8584 for example is composed of 4 PHYs. With
hardware packages, parts of the logic is usually common and one of the
PHY has to be used for some parts of the initialization. Following this
logic, the 1588 blocks of those PHYs are shared between two PHYs and
accessing the registers has to be done using the "base" PHY of the
group. This is handled thanks to helpers in the PTP code (and locks).
We also need the MDIO bus lock while performing a single read or write
to the 1588 registers as the read/write are composed of multiple MDIO
transactions (and we don't want other threads updating the page).
Co-developed-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| 4c8c5dc5 | 23-Jun-2020 |
Antoine Tenart <antoine.tenart@bootlin.com> |
net: phy: mscc: take into account the 1588 block in MACsec init
This patch takes in account the use of the 1588 block in the MACsec
initialization, as a conditional configuration has to be done (whe
net: phy: mscc: take into account the 1588 block in MACsec init
This patch takes in account the use of the 1588 block in the MACsec
initialization, as a conditional configuration has to be done (when the
1588 block is used).
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| 6705b58d | 23-Jun-2020 |
Quentin Schulz <quentin.schulz@bootlin.com> |
net: phy: mscc: remove the TR CLK disable magic value
This patch adds a define for the 0x8000 magic value used to perform
enable/disable actions on the "token ring clock". The patch is only
cosmetic
net: phy: mscc: remove the TR CLK disable magic value
This patch adds a define for the 0x8000 magic value used to perform
enable/disable actions on the "token ring clock". The patch is only
cosmetic.
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| 49113d5e | 05-Jun-2020 |
Antoine Tenart <antoine.tenart@bootlin.com> |
net: phy: mscc: fix Serdes configuration in vsc8584_config_init
When converting the MSCC PHY driver to shared PHY packages, the Serdes
configuration in vsc8584_config_init was modified to use 'base_
net: phy: mscc: fix Serdes configuration in vsc8584_config_init
When converting the MSCC PHY driver to shared PHY packages, the Serdes
configuration in vsc8584_config_init was modified to use 'base_addr'
instead of 'base' as the port number. But 'base_addr' isn't equal to
'addr' for all PHYs inside the package, which leads to the Serdes still
being enabled on those ports. This patch fixes it.
Fixes: deb04e9c0ff2 ("net: phy: mscc: use phy_package_shared")
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| d3169863 | 19-Mar-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
net: phy: mscc: add support for VSC8502
This is a dual copper PHY with support for MII/GMII/RGMII on MAC side,
as well as a bunch of other features such as SyncE and Ring Resiliency.
I haven't test
net: phy: mscc: add support for VSC8502
This is a dual copper PHY with support for MII/GMII/RGMII on MAC side,
as well as a bunch of other features such as SyncE and Ring Resiliency.
I haven't tested interrupts and WoL, but I am confident that they work
since support is already present in the driver and the register map is
no different for this PHY.
PHY statistics work, PHY tunables appear to work, suspend/resume works.
Signed-off-by: Wes Li <wes.li@nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| 7b005a17 | 19-Mar-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
net: phy: mscc: configure both RX and TX internal delays for RGMII
The driver appears to be secretly enabling the RX clock skew
irrespective of PHY interface type, which is generally considered a bi
net: phy: mscc: configure both RX and TX internal delays for RGMII
The driver appears to be secretly enabling the RX clock skew
irrespective of PHY interface type, which is generally considered a big
no-no.
Make them configurable instead, and add TX internal delays when
necessary too.
While at it, configure a more canonical clock skew of 2.0 nanoseconds
than the current default of 1.1 ns.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| da206d65 | 19-Mar-2020 |
Vladimir Oltean <vladimir.oltean@nxp.com> |
net: phy: mscc: accept all RGMII species in vsc85xx_mac_if_set
The helper for configuring the pinout of the MII side of the PHY should
do so irrespective of whether RGMII delays are used or not. So
net: phy: mscc: accept all RGMII species in vsc85xx_mac_if_set
The helper for configuring the pinout of the MII side of the PHY should
do so irrespective of whether RGMII delays are used or not. So accept
the ID, TXID and RXID variants as well, not just the no-delay RGMII
variant.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| dee48f78 | 19-Mar-2020 |
Antoine Tenart <antoine.tenart@bootlin.com> |
net: phy: mscc: RGMII skew delay configuration
This patch adds support for configuring the RGMII skew delays in Rx and
Tx. The Rx and Tx skews are set based on the interface mode. By default
their c
net: phy: mscc: RGMII skew delay configuration
This patch adds support for configuring the RGMII skew delays in Rx and
Tx. The Rx and Tx skews are set based on the interface mode. By default
their configuration is set to the default value in hardware (0.2ns);
this means the driver do not rely anymore on the bootloader
configuration.
Then based on the interface mode being used, a 2ns delay is added:
- RGMII_ID adds it for both Rx and Tx.
- RGMII_RXID adds it for Rx.
- RGMII_TXID adds it for Tx.
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| c4474fe1 | 16-Mar-2020 |
Heiner Kallweit <hkallweit1@gmail.com> |
net: phy: mscc: consider interrupt source in interrupt handler
Trigger the respective interrupt handler functionality only if the
related interrupt source bit is set.
Signed-off-by: Heiner Kallweit
net: phy: mscc: consider interrupt source in interrupt handler
Trigger the respective interrupt handler functionality only if the
related interrupt source bit is set.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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