Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and 'clk-rockchip' into clk-next

* clk-renesas:
clk: renesas: rcar-gen3: Add HS400 quirk for SD clock
clk: renesas: rcar-g

Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and 'clk-rockchip' into clk-next

* clk-renesas:
clk: renesas: rcar-gen3: Add HS400 quirk for SD clock
clk: renesas: rcar-gen3: Add documentation for SD clocks
clk: renesas: rcar-gen3: Set state when registering SD clocks
clk: renesas: r8a77995: Simplify PLL3 multiplier/divider
clk: renesas: r8a77995: Add missing CPEX clock
clk: renesas: r8a77995: Remove non-existent SSP clocks
clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocks
clk: renesas: r8a77995: Correct parent clock of DU
clk: renesas: r8a77990: Correct parent clock of DU
clk: renesas: r8a77970: Add CPEX clock
clk: renesas: r8a77965: Add CPEX clock
clk: renesas: r8a7796: Add CPEX clock
clk: renesas: r8a7795: Add CPEX clock
clk: renesas: r8a774a1: Add CPEX clock
dt-bindings: clock: r8a7796: Remove CSIREF clock
dt-bindings: clock: r8a7795: Remove CSIREF clock
clk: renesas: Mark rza2_cpg_clk_register static
clk: renesas: r7s9210: Add USB clocks
clk: renesas: r8a77970: Add RPC clocks
clk: renesas: r7s9210: Add SDHI clocks

* clk-allwinner:
clk: sunxi-ng: a64: Allow parent change for VE clock
clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocks
clk: sunxi-ng: a33: Use sigma-delta modulation for audio PLL
clk: sunxi-ng: h3: Allow parent change for ve clock
clk: sunxi-ng: add support for suniv F1C100s SoC
dt-bindings: clock: Add Allwinner suniv F1C100s CCU
clk: sunxi-ng: h3/h5: Fix CSI_MCLK parent
clk: sunxi-ng: r40: Force LOSC parent to RTC LOSC output
clk: sunxi-ng: sun50i: a64: Use sigma-delta modulation for audio PLL
clk: sunxi-ng: a64: Fix gate bit of DSI DPHY
clk: sunxi-ng: Enable DE2_CCU for SUN8I and SUN50I
clk: sunxi-ng: Add support for H6 DE3 clocks
dt-bindings: clock: sun8i-de2: Add H6 DE3 clock description
clk: sunxi-ng: h6: Set video PLLs limits
clk: sunxi-ng: Use u64 for calculation of NM rate
clk: sunxi-ng: Adjust MP clock parent rate when allowed
clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width
clk: sunxi-ng: enable so-said LDOs for A64 SoC's pll-mipi clock

* clk-tegra:
clk: tegra: Return the exact clock rate from clk_round_rate
clk: tegra30: Use Tegra CPU powergate helper function
soc/tegra: pmc: Drop SMP dependency from CPU APIs
clk: tegra: Fix maximum audio sync clock for Tegra124/210
clk: tegra: get rid of duplicate defines
clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC
clk: tegra20: Turn EMC clock gate into divider

* clk-meson: (25 commits)
clk: meson: axg-audio: use the clk input helper function
clk: meson: add clk-input helper function
clk: meson: Mark some things static
clk: meson: meson8b: add the read-only video clock trees
clk: meson: meson8b: add the fractional divider for vid_pll_dco
clk: meson: meson8b: fix the offset of vid_pll_dco's N value
clk: meson: Fix GXL HDMI PLL fractional bits width
clk: meson: meson8b: add the CPU clock post divider clocks
clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3
clk: meson: clk-regmap: add read-only gate ops
clk: meson: meson8b: allow changing the CPU clock tree
clk: meson: meson8b: run from the XTAL when changing the CPU frequency
clk: meson: meson8b: add support for more M/N values in sys_pll
clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICAL
clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_sel
clk: meson: clk-pll: check if the clock is already enabled
clk: meson: meson8b: fix the width of the cpu_scale_div clock
clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_table
clk: meson: meson8b: use the HHI syscon if available
dt-bindings: clock: meson8b: use the registers from the HHI syscon
...

* clk-rockchip:
clk: rockchip: add clock-id to gate of ACODEC for rk3328
clk: rockchip: add clock ID of ACODEC for rk3328
clk: rockchip: fix ID of 8ch clock of I2S1 for rk3328
clk: rockchip: fix I2S1 clock gate register for rk3328
clk: rockchip: make rk3188 hclk_vio_bus critical
clk: rockchip: fix rk3188 sclk_mac_lbtest parameter ordering
clk: rockchip: fix rk3188 sclk_smc gate data
clk: rockchip: fix typo in rk3188 spdif_frac parent

show more ...

Merge tag 'meson-clk-4.21-2' of https://github.com/BayLibre/clk-meson into clk-meson

Pull more meson clk driver updates from Neil Armstrong:

- Fix GXL HDMI Pll fractional bits (from first round)

Merge tag 'meson-clk-4.21-2' of https://github.com/BayLibre/clk-meson into clk-meson

Pull more meson clk driver updates from Neil Armstrong:

- Fix GXL HDMI Pll fractional bits (from first round)
- Add the Meson8/Meson8b video clocks
- Add clk-input helper and use it for axg-audio clock driver

* tag 'meson-clk-4.21-2' of https://github.com/BayLibre/clk-meson:
clk: meson: axg-audio: use the clk input helper function
clk: meson: add clk-input helper function
clk: meson: meson8b: add the read-only video clock trees
clk: meson: meson8b: add the fractional divider for vid_pll_dco
clk: meson: meson8b: fix the offset of vid_pll_dco's N value
clk: meson: Fix GXL HDMI PLL fractional bits width

show more ...

clk: meson: add clk-input helper function

Add the clock input helper function. Several amlogic clock controllers
will now be registering bypass clock input. Instead of copying this
code in every of

clk: meson: add clk-input helper function

Add the clock input helper function. Several amlogic clock controllers
will now be registering bypass clock input. Instead of copying this
code in every of them, let's make an helper function for it

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
[narmstrong: fixed up to apply on Makefile and clkc.h]
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20181204165819.21541-2-jbrunet@baylibre.com

show more ...

Merge tag 'meson-clk-4.21-1' of https://github.com/BayLibre/clk-meson into clk-meson

Pull amlogic meson clk driver updates from Neil Armstrong:

- Add GX video clocks
- Switch to HHI syscon for me

Merge tag 'meson-clk-4.21-1' of https://github.com/BayLibre/clk-meson into clk-meson

Pull amlogic meson clk driver updates from Neil Armstrong:

- Add GX video clocks
- Switch to HHI syscon for meson8b
- Fix meson8b cpu clock
- Add support for meson8b CPU scaling
- Add Meson8b CPU post-dividers clocks

* tag 'meson-clk-4.21-1' of https://github.com/BayLibre/clk-meson:
clk: meson: meson8b: add the CPU clock post divider clocks
clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3
clk: meson: clk-regmap: add read-only gate ops
clk: meson: meson8b: allow changing the CPU clock tree
clk: meson: meson8b: run from the XTAL when changing the CPU frequency
clk: meson: meson8b: add support for more M/N values in sys_pll
clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICAL
clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_sel
clk: meson: clk-pll: check if the clock is already enabled
clk: meson: meson8b: fix the width of the cpu_scale_div clock
clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_table
clk: meson: meson8b: use the HHI syscon if available
dt-bindings: clock: meson8b: use the registers from the HHI syscon
clk: meson-gxbb: Add video clocks
dt-bindings: clk: meson-gxbb: Add Video clock bindings
clk: meson-gxbb: Fix HDMI PLL for GXL SoCs
clk: meson: Add vid_pll divider driver
dt-bindings: clock: meson8b: export the CPU post dividers

show more ...

clk: meson: Add vid_pll divider driver

Add support the VID_PLL fully programmable divider used right after the
HDMI PLL clock source. It is used to achieve complex fractional division
with a program

clk: meson: Add vid_pll divider driver

Add support the VID_PLL fully programmable divider used right after the
HDMI PLL clock source. It is used to achieve complex fractional division
with a programmble bitfield.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Link: http://lkml.kernel.org/r/1541516257-16157-2-git-send-email-narmstrong@baylibre.com

show more ...

Merge tag 'v4.19-rc5' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into fbdev-for-next

Sync with upstream (which now contains fbdev-v4.19 changes) to
prepare a base for fbdev-v4

Merge tag 'v4.19-rc5' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into fbdev-for-next

Sync with upstream (which now contains fbdev-v4.19 changes) to
prepare a base for fbdev-v4.20 changes.

show more ...

Merge drm/drm-next into drm-intel-next-queued

Catch up in general, and get DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT
specifically.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Merge tag 'y2038' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/playground into timers/core

Pull more y2038 work from Arnd Bergman:

y2038: convert more syscalls

Here is another set of syst

Merge tag 'y2038' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/playground into timers/core

Pull more y2038 work from Arnd Bergman:

y2038: convert more syscalls

Here is another set of system call changes to prepare the change over to
64-bit time_t. As before, the strategy is to change system calls that
take a 'struct timespec' argument over to 'struct __kernel_timespec',
which for now is defined to be the same but will get redefined to use a
64-bit time_t argument once we are ready to modify the system call tables.

The major change from previous patches is that the plan is no longer
to directly use the 'compat' system calls for providing compatibility
with the existing 32-bit time_t based entry points. Instead, we rename
the compat code to something that makes more sense on 32-bit architectures,
e.g. compat_timespec becomes old_timespec32.

With the renamed types in place, change over the 'stat' and 'utimes'
families of system calls, sched_rr_get_interval, recvmmsg and
rt_sigtimedwait. Another series for poll, select and io_pgetevents is
currently being tested.

show more ...

Merge tag 'v4.19-rc2' into next-general

Sync to Linux 4.19-rc2 for downstream developers.

Merge tag 'v4.19-rc1' into asoc-4.19

Linux 4.19-rc1

Merge branch 'perm-fix' into omap-for-v4.19/fixes-v2

Merge drm/drm-next into drm-misc-next

Now that 4.19-rc1 is cut, backmerge it into -misc-next.

Signed-off-by: Sean Paul <seanpaul@chromium.org>

Merge branch 'for-4.19/cougar' into for-linus

New device support for hid-cougar

Merge branch 'linus/master' into rdma.git for-next

rdma.git merge resolution for the 4.19 merge window

Conflicts:
drivers/infiniband/core/rdma_core.c
- Use the rdma code and revise with the new

Merge branch 'linus/master' into rdma.git for-next

rdma.git merge resolution for the 4.19 merge window

Conflicts:
drivers/infiniband/core/rdma_core.c
- Use the rdma code and revise with the new spelling for
atomic_fetch_add_unless
drivers/nvme/host/rdma.c
- Replace max_sge with max_send_sge in new blk code
drivers/nvme/target/rdma.c
- Use the blk code and revise to use NULL for ib_post_recv when
appropriate
- Replace max_sge with max_recv_sge in new blk code
net/rds/ib_send.c
- Use the net code and revise to use NULL for ib_post_recv when
appropriate

Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>

show more ...

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
"The new and exciting feature this time around is in the clk core.
We've a

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
"The new and exciting feature this time around is in the clk core.
We've added duty cycle support to the clk API so that clk signal duty
cycle ratios can be adjusted while taking into account things like clk
dividers and clk tree hierarchy. So far only one SoC has implemented
support for this, but I expect there will be more to come in the
future.

Outside of the core, we have the usual pile of clk driver updates and
additions. The Amlogic meson driver got the most lines in the diffstat
this time around because it added support for a whole bunch of
hardware and duty cycle configuration. After that the Rockchip PX30,
Qualcomm SDM845, and Renesas SoC drivers fill in a majority of the
diff. We're left with the collection of non-critical fixes after that.
Overall it looks pretty quiet this time.

Core:
- Clk duty cycle support
- Proper CLK_SET_RATE_GATE support throughout the tree

New Drivers:
- Actions Semi Owl series S700 SoC clk driver
- Qualcomm SDM845 display clock controller
- i.MX6SX ocram_s clk support
- Uniphier NAND, USB3 PHY, and SPI clk support
- Qualcomm RPMh clk driver
- i.MX7D mailbox clk support
- Maxim 9485 Programmable Clock Generator
- expose 32 kHz PLL on PXA SoCs
- imx6sll GPIO clk gate support
- Atmel at91 I2S audio clk support
- SI544/SI514 clk on/off support
- i.MX6UL GPIO clock gates in CCM CCGR
- Renesas Crypto Engine clocks on R-Car H3
- Renesas clk support for the new RZ/N1D SoC
- Allwinner A64 display engine clock support
- support for Rockchip's PX30 SoC
- Amlogic Meson axg PCIe and audio clocks
- Amlogic Meson GEN CLK on gxbb, gxl and axg

Updates:
- remove an unused variable from Exynos4412 ISP driver
- fix a thinko bug in SCMI clk division logic
- add missing of_node_put()s in some i.MX clk drivers
- Tegra SDMMC clk jitter improvements with high speed signaling modes
- SPDX tagging for qcom and cs2000-cp drivers
- stop leaking con ids in __clk_put()
- fix a corner case in fixed factor clk probing where node is in DT
but parent clk is registered much later
- Marvell Armada 3700 clk_pm_cpu_get_parent() had an invalid return
value
- i.MX clk init arrays removed in place of CLK_IS_CRITICAL
- convert to CLK_IS_CRITICAL for i.MX51/53 driver
- fix Tegra BPMP driver oops when xlating a NULL clk
- proper default configuration for vic03 and vde clks on Tegra124
- mark Tegra memory controller clks as critical
- fix array bounds clamp in Tegra's emc determine_rate() op
- Ingenic i2s bit update and allow UDC clk to gate
- fix name of aspeed SDC clk define to have only one 'CLK'
- fix i.MX6QDL video clk parent
- critical clk markings for qcom SDM845
- fix Stratix10 mpu_free_clk and sdmmc_free_clk parents
- mark Rockchip's pclk_rkpwm_pmu as critical clock, due to it
supplying the pwm used to drive the logic supply of the rk3399
core"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (85 commits)
clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399
clk: cs2000-cp: convert to SPDX identifiers
clk: scmi: Fix the rounding of clock rate
clk: qcom: Add display clock controller driver for SDM845
clk: mvebu: armada-37xx-periph: Remove unused var num_parents
clk: samsung: Remove unused mout_user_aclk400_mcuisp_p4x12 variable
clk: actions: Add S700 SoC clock support
dt-bindings: clock: Add S700 support for Actions Semi Soc's
clk: actions: Add missing REGMAP_MMIO dependency
clk: uniphier: add clock frequency support for SPI
clk: uniphier: add more USB3 PHY clocks
clk: uniphier: add NAND 200MHz clock
clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks
clk: tegra: Add sdmmc mux divider clock
clk: tegra: Refactor fractional divider calculation
clk: tegra: Fix includes required by fence_udelay()
clk: imx6sll: fix missing of_node_put()
clk: imx6ul: fix missing of_node_put()
clk: imx: add ocram_s clock for i.mx6sx
clk: mvebu: armada-37xx-periph: Fix wrong return value in get_parent
...

show more ...

Merge branches 'clk-mvebu-spdx', 'clk-meson', 'clk-imx7d-mu', 'clk-imx-init-array-cleanup' and 'clk-rockchip' into clk-next

* clk-mvebu-spdx:
clk: mvebu: armada-37xx-periph: switch to SPDX license

Merge branches 'clk-mvebu-spdx', 'clk-meson', 'clk-imx7d-mu', 'clk-imx-init-array-cleanup' and 'clk-rockchip' into clk-next

* clk-mvebu-spdx:
clk: mvebu: armada-37xx-periph: switch to SPDX license identifier

* clk-meson:
clk: meson: add gen_clk
clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition
clk: meson-axg: add clocks required by pcie driver
clk: meson: remove unused clk-audio-divider driver
clk: meson: stop rate propagation for audio clocks
clk: meson: axg: add the audio clock controller driver
clk: meson: add axg audio sclk divider driver
clk: meson: add triple phase clock driver
clk: meson: add clk-phase clock driver
clk: meson: clean-up meson clock configuration
clk: meson: remove obsolete register access
clk: meson: expose GEN_CLK clkid
clk: meson-axg: add pcie and mipi clock bindings
dt-bindings: clock: add meson axg audio clock controller bindings
clk: meson: audio-divider is one based
clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL

* clk-imx7d-mu:
: - i.MX7D mailbox clk support
clk: imx7d: add IMX7D_MU_ROOT_CLK

* clk-imx-init-array-cleanup:
: - i.MX clk init arrays removed in place of CLK_IS_CRITICAL
clk: imx6sx: remove clks_init_on array
clk: imx6sl: remove clks_init_on array
clk: imx6q: remove clks_init_on array

* clk-rockchip:
clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399
clk: rockchip: fix clk_i2sout parent selection bits on rk3399
clk: rockchip: add clock controller for px30
clk: rockchip: add support for half divider
dt-bindings: add bindings for px30 clock controller
clk: rockchip: add dt-binding header for px30

show more ...

Merge drm/drm-next into drm-intel-next-queued

We need a backmerge to get DP_DPCD_REV_14 before we push other
i915 changes to dinq that could break compilation.

Signed-off-by: Rodrigo Vivi <rodrigo.

Merge drm/drm-next into drm-intel-next-queued

We need a backmerge to get DP_DPCD_REV_14 before we push other
i915 changes to dinq that could break compilation.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

show more ...

Merge tag 'meson-clk-4.19-1' of https://github.com/BayLibre/clk-meson into clk-meson

Pull first round of updates for meson clocks from Jerome Brunet:

- Remove legacy register access (finish moving

Merge tag 'meson-clk-4.19-1' of https://github.com/BayLibre/clk-meson into clk-meson

Pull first round of updates for meson clocks from Jerome Brunet:

- Remove legacy register access (finish moving to syscon)
- Clean up configuration flags
- Add axg PCIe clocks
- Add GEN CLK on gxbb, gxl and axg
- Remove clk_audio_divider driver
- Add axg audio clock controller

* tag 'meson-clk-4.19-1' of https://github.com/BayLibre/clk-meson:
clk: meson: add gen_clk
clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition
clk: meson-axg: add clocks required by pcie driver
clk: meson: remove unused clk-audio-divider driver
clk: meson: stop rate propagation for audio clocks
clk: meson: axg: add the audio clock controller driver
clk: meson: add axg audio sclk divider driver
clk: meson: add triple phase clock driver
clk: meson: add clk-phase clock driver
clk: meson: clean-up meson clock configuration
clk: meson: remove obsolete register access
clk: meson: expose GEN_CLK clkid
clk: meson-axg: add pcie and mipi clock bindings
dt-bindings: clock: add meson axg audio clock controller bindings
clk: meson: audio-divider is one based
clk: add duty cycle support
clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL

show more ...

clk: meson: remove unused clk-audio-divider driver

clk-audio-divider is no longer used, we can remove it.

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@ba

clk: meson: remove unused clk-audio-divider driver

clk-audio-divider is no longer used, we can remove it.

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

show more ...

clk: meson: axg: add the audio clock controller driver

The axg audio clock controller is the clock generation unit for the
amlogic audio subsystem of A113 based SoCs. It may be clocked by 8
differen

clk: meson: axg: add the audio clock controller driver

The axg audio clock controller is the clock generation unit for the
amlogic audio subsystem of A113 based SoCs. It may be clocked by 8
different plls provided by the primary clock controller and also by
10 slave bit clocks and 10 slave sample clocks which may be provided
by external components, such as audio codecs, through the SoC pads.

It contains several muxes, dividers and gates which are fed into the
the different devices of the audio subsystem.

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

show more ...

clk: meson: add axg audio sclk divider driver

Add a driver to control the clock divider found in the sample clock
generator of the axg audio clock controller.

The sclk divider accumulates specific

clk: meson: add axg audio sclk divider driver

Add a driver to control the clock divider found in the sample clock
generator of the axg audio clock controller.

The sclk divider accumulates specific features which make the generic
divider unsuitable to control it:
- zero based divider (div = val + 1), but zero value gates the clock,
so minimum divider value is 2.
- lrclk variant may adjust the duty cycle depending the divider value
and the 'hi' value.

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

show more ...

clk: meson: add triple phase clock driver

Add a driver to control the output of the sample clock generator found
in the axg audio clock controller.

The goal of this driver is to coherently control

clk: meson: add triple phase clock driver

Add a driver to control the output of the sample clock generator found
in the axg audio clock controller.

The goal of this driver is to coherently control the phase provided to
the different element using the sample clock generator. This simplify
the usage of the sample clock generator a lot, without comprising the
ability of the SoC.

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

show more ...

clk: meson: add clk-phase clock driver

Add a driver based meson clk-regmap to control clock phase on
amlogic SoCs

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jb

clk: meson: add clk-phase clock driver

Add a driver based meson clk-regmap to control clock phase on
amlogic SoCs

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

show more ...

Merge tag 'v4.18-rc2' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into fbdev-for-next

Linux 4.18-rc2

Merge tag 'v4.18-rc2' into next-general

Merge to Linux 4.18-rc2 for security subsystem developers.