Merge remote-tracking branch 'torvalds/master' into perf/core

To pick up some tools/perf/ patches that went via tip/perf/core, such
as:

tools/perf: Add mem_hops field in perf_mem_data_src structu

Merge remote-tracking branch 'torvalds/master' into perf/core

To pick up some tools/perf/ patches that went via tip/perf/core, such
as:

tools/perf: Add mem_hops field in perf_mem_data_src structure

Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
"The usual collection of clk driver updates and new driver additions.
In t

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
"The usual collection of clk driver updates and new driver additions.
In terms of lines it's mainly Qualcomm and Mediatek code, supporting
various SoCs and their multitude of clk controllers.

New Drivers:
- GCC and RPMcc support for Qualcomm QCM2290 SoCs
- GCC support for Qualcomm MSM8994/MSM8992 SoCs
- LPASSCC and CAMCC support for Qualcomm SC7280 SoCs
- Support for Mediatek MT8195 SoCs
- Initial clock driver for the Exynos850 SoC
- Add i.MX8ULP clock driver and related bindings

Updates:
- Clock power management for new SAMA7G5 SoC
- Updates to the master clock driver and sam9x60-pll to be able to
use cpufreq-dt driver and avoid overclocking of CPU and MCK0
domains while changing the frequency via DVFS
- Use ARRAY_SIZE in qcom clk drivers
- Remove some impractical fallback parent names in qcom clk drivers
- Make Mediatek clk drivers tristate
- Refactoring of the CPU clock code and conversion of Samsung
Exynos5433 CPU clock driver to the platform driver
- A few conversions to devm_platform_ioremap_resource()
- Updates of the Samsung Kconfig help text
- Update video path realted clocks for Amlogic meson8
- Add SPI Multi I/O Bus and SDHI clocks and resets on Renesas RZ/G2L
- Add SPI Multi I/O Bus (RPC) clocks on Renesas R-Car V3U
- Add MediaLB clocks on Renesas R-Car H3, M3-W/W+, and M3-N
- Remove unused helpers from i.MX specific clock header
- Rework all i.MX clk based helpers to use clk_hw based ones
- Rework i.MX gate/mux/divider wrappers
- Rework imx_clk_hw_composite and imx_clk_hw_pll14xx wrappers
- Update i.MX pllv4 and composite clocks to support i.MX8ULP
- Disable i.MX7ULP composite clock during initialization
- Add CLK_SET_RATE_NO_REPARENT flag to the i.MX7ULP composite
- Disable the i.MX pfd when set pfdv2 clock rate
- Add support for i.MX8ULP in pfdv2
- Add the pcc reset controller support on i.MX8ULP
- Fix the build break when clk-imx8ulp is built as module
- Move csi_sel mux to correct base register in i.MX6UL clock drivr
- Fix csi clk gate register in i.MX6UL clock driver
- Fix build bug making CLK_IMX8ULP select MXC_CLK
- Add TPU (PWM), and Z (Cortex-A76) clocks on Renesas R-Car V3U
- Add Ethernet clocks on Renesas RZ/G2L
- Move Rockchip to use module_platform_probe
- Enable usage of Coresight related clocks on Rockchip rk3399"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (170 commits)
clk: use clk_core_get_rate_recalc() in clk_rate_get()
clk: at91: sama7g5: set low limit for mck0 at 32KHz
clk: at91: sama7g5: remove prescaler part of master clock
clk: at91: clk-master: add notifier for divider
clk: at91: clk-sam9x60-pll: add notifier for div part of PLL
clk: at91: clk-master: fix prescaler logic
clk: at91: clk-master: mask mckr against layout->mask
clk: at91: clk-master: check if div or pres is zero
clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULL
clk: at91: pmc: add sama7g5 to the list of available pmcs
clk: at91: clk-master: improve readability by using local variables
clk: at91: clk-master: add register definition for sama7g5's master clock
clk: at91: sama7g5: add securam's peripheral clock
clk: at91: pmc: execute suspend/resume only for backup mode
clk: at91: re-factor clocks suspend/resume
clk: ux500: Add driver for the reset portions of PRCC
dt-bindings: clock: u8500: Rewrite in YAML and extend
clk: composite: Use rate_ops.determine_rate when also a mux is available
clk: samsung: describe drivers in Kconfig
clk: samsung: exynos5433: update apollo and atlas clock probing
...

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Merge branches 'clk-qcom', 'clk-mtk', 'clk-versatile' and 'clk-doc' into clk-next

- Use ARRAY_SIZE in qcom clk drivers
- Remove some impractical fallback parent names in qcom clk drivers
- GCC an

Merge branches 'clk-qcom', 'clk-mtk', 'clk-versatile' and 'clk-doc' into clk-next

- Use ARRAY_SIZE in qcom clk drivers
- Remove some impractical fallback parent names in qcom clk drivers
- GCC and RPMcc support for Qualcomm QCM2290 SoCs
- GCC support for Qualcomm MSM8994/MSM8992 SoCs
- LPASSCC and CAMCC support for Qualcomm SC7280 SoCs
- Support for Mediatek MT8195 SoCs
- Make Mediatek clk drivers tristate

* clk-qcom: (44 commits)
clk: qcom: gdsc: enable optional power domain support
clk: qcom: videocc-sm8250: use runtime PM for the clock controller
clk: qcom: dispcc-sm8250: use runtime PM for the clock controller
dt-bindings: clock: qcom,videocc: add mmcx power domain
dt-bindings: clock: qcom,dispcc-sm8x50: add mmcx power domain
clk: qcom: gcc-sc7280: Drop unused array
clk: qcom: camcc: Add camera clock controller driver for SC7280
dt-bindings: clock: Add YAML schemas for CAMCC clocks on SC7280
clk: qcom: Add lpass clock controller driver for SC7280
dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280
clk: qcom: Kconfig: Sort the symbol for SC_LPASS_CORECC_7180
clk: qcom: mmcc-sdm660: Add hw_ctrl flag to venus_core0_gdsc
clk: qcom: mmcc-sdm660: Add necessary CXCs to venus_gdsc
clk: qcom: gcc-msm8994: Use ARRAY_SIZE() for num_parents
clk: qcom: gcc-msm8994: Add proper msm8992 support
clk: qcom: gcc-msm8994: Add modem reset
clk: qcom: gcc-msm8994: Remove the inexistent GDSC_PCIE
clk: qcom: gcc-msm8994: Add missing clocks
clk: qcom: gcc-msm8994: Add missing NoC clocks
clk: qcom: gcc-msm8994: Fix up SPI QUP clocks
...

* clk-mtk: (28 commits)
clk: mediatek: Export clk_ops structures to modules
clk: mediatek: support COMMON_CLK_MT6779 module build
clk: mediatek: support COMMON_CLK_MEDIATEK module build
clk: composite: export clk_register_composite
clk: mediatek: Add MT8195 apusys clock support
clk: mediatek: Add MT8195 imp i2c wrapper clock support
clk: mediatek: Add MT8195 wpesys clock support
clk: mediatek: Add MT8195 vppsys1 clock support
clk: mediatek: Add MT8195 vppsys0 clock support
clk: mediatek: Add MT8195 vencsys clock support
clk: mediatek: Add MT8195 vdosys1 clock support
clk: mediatek: Add MT8195 vdosys0 clock support
clk: mediatek: Add MT8195 vdecsys clock support
clk: mediatek: Add MT8195 scp adsp clock support
clk: mediatek: Add MT8195 mfgcfg clock support
clk: mediatek: Add MT8195 ipesys clock support
clk: mediatek: Add MT8195 imgsys clock support
clk: mediatek: Add MT8195 ccusys clock support
clk: mediatek: Add MT8195 camsys clock support
clk: mediatek: Add MT8195 infrastructure clock support
...

* clk-versatile:
clk: versatile: hide clock drivers from non-ARM users
clk: versatile: Rename ICST to CLK_ICST
clk: versatile: clk-icst: Support 'reg' in addition to 'vco-offset' for register address
dt-bindings: clock: arm,syscon-icst: Use 'reg' instead of 'vco-offset' for VCO register address

* clk-doc:
dt-bindings: clk: fixed-mmio-clock: Convert to YAML

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clk: mediatek: Add MT8195 infrastructure clock support

Add MT8195 infrastructure clock controller which provides
clock gate control for basic IP like pwm, uart, spi and so on.

Signed-off-by: Chun-J

clk: mediatek: Add MT8195 infrastructure clock support

Add MT8195 infrastructure clock controller which provides
clock gate control for basic IP like pwm, uart, spi and so on.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210914021633.26377-10-chun-jie.chen@mediatek.com
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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