clk: mediatek: Make mtk_clk_simple_remove() return void

__mtk_clk_simple_remove() and so also mtk_clk_simple_remove() return
zero unconditionally. Make them return no value instead and convert the
d

clk: mediatek: Make mtk_clk_simple_remove() return void

__mtk_clk_simple_remove() and so also mtk_clk_simple_remove() return
zero unconditionally. Make them return no value instead and convert the
drivers making use of it to platform_driver's .remove_new().

This makes the semantics in the callers of mtk_clk_simple_remove() clearer
and prepares for the quest to make platform driver's remove function return
void. There is no semantic change.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20230430190233.878921-2-u.kleine-koenig@pengutronix.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

show more ...

Merge drm/drm-next into drm-misc-next

Start the 6.5 release cycle.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>

Merge branch 'next' into for-linus

Prepare input updates for 6.4 merge window.

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
"Nothing looks out of the ordinary in this batch of clk driver updates.

T

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
"Nothing looks out of the ordinary in this batch of clk driver updates.

There are a couple patches to the core clk framework, but they're all
basically cleanups or debugging aids. The driver updates and new
additions are dominated in the diffstat by Qualcomm and MediaTek
drivers. Qualcomm gained a handful of new drivers for various SoCs,
and MediaTek gained a bunch of drivers for MT8188. The MediaTek
drivers are being modernized as well, so there are updates all over
that vendor's clk drivers. There's also a couple other new clk drivers
in here, for example the Starfive JH7110 SoC support is added.

Outside of the two major SoC vendors though, we have the usual
collection of non-critical fixes and cleanups to various clk drivers.
It's good to see that we're getting more cleanups and modernization
patches. Maybe one day we'll be able to properly split clk providers
from clk consumers.

Core:
- Print an informational message before disabling unused clks

New Drivers:
- BCM63268 timer clock and reset controller
- Frequency Hopping (FHCTL) on MediaTek MT6795, MT8173, MT8192 and
MT8195 SoCs
- Mediatek MT8188 SoC clk drivers
- Clock driver for Sunplus SP7021 SoC
- Clk driver support for Loongson-2 SoCs
- Clock driver for Skyworks Si521xx I2C PCIe clock generators
- Initial Starfive JH7110 clk/reset support
- Global clock controller drivers for Qualcomm SM7150, IPQ9574,
MSM8917 and IPQ5332 SoCs
- GPU clock controller drivers for SM6115, SM6125, SM6375 and SA8775P
SoCs

Updates:
- Shrink size of clk_fractional_divider a little
- Convert various clk drivers to devm_of_clk_add_hw_provider()
- Convert platform clk drivers to remove_new()
- Converted most Mediatek clock drivers to struct platform_driver
- MediaTek clock drivers can be built as modules
- Reimplement Loongson-1 clk driver with DT support
- Migrate socfpga clk driver to of_clk_add_hw_provider()
- Support for i3c clks on Aspeed ast2600 SoCs
- Add clock generic devm_clk_hw_register_gate_parent_data
- Add audiomix block control for i.MX8MP
- Add support for determine_rate to i.MX composite-8m
- Let the LCDIF Pixel clock of i.MX8MM and i.MX8MN set parent rate
- Provide clock name in error message for clk-gpr-mux on get parent
failure
- Drop duplicate imx_clk_mux_flags macro
- Register the i.MX8MP Media Disp2 Pix clock as bus clock
- Add Media LDB root clock to i.MX8MP
- Make i.MX8MP nand_usdhc_bus clock as non-critical
- Fix the rate table for i.MX fracn-gppll
- Disable HW control for the fracn-gppll in order to be controlled by
register write
- Add support for interger PLL in fracn-gppll
- Add mcore_booted module parameter to i.MX93 provider
- Add NIC, A55 and ARM PLL clocks to i.MX93
- Fix i.MX8ULP XBAR_DIVBUS and AD_SLOW clock parents
- Use "divider closest" clock type for PLL4_PFD dividers on i.MX8ULP
to get more accurate clock rates
- Mark the MU0_Bi and TPM5 clocks on i.MX8ULP as critical
- Update some of the i.MX critical clocks flags to allow glitchless
on-the-fly rate change.
- Add I2C5 clock on Renesas R-Car V3H
- Exynos850: Add CMU_G3D clock controller for the Mali GPU
- Extract Exynos5433 (ARM64) clock controller power management code
to common driver parts
- Exynos850: make PMU_ALIVE_PCLK clock critical
- Add Audio, thermal, camera (CSI-2), Image Signal Processor/Channel
Selector (ISPCS), and video capture (VIN) clocks on Renesas R-Car
V4H
- Add video capture (VIN) clocks on Renesas R-Car V3H
- Add Cortex-A53 System CPU (Z2) clocks on Renesas R-Car V3M and V3H
- Support for Stromer Plus PLL on Qualcomm IPQ5332
- Add a missing reset to Qualcomm QCM2290
- Migrate Qualcomm IPQ4019 to clk_parent_data
- Make USB GDSCs enter retention state when disabled on Qualcomm
SM6375, MSM8996 and MSM8998 SoCs
- Set floor rounding clk_ops for Qualcomm QCM2290 SDCC2 clk
- Add two EMAC GDSCs on Qualcomm SC8280XP
- Use shared rcg clk ops in Qualcomm SM6115 GCC
- Park Qualcomm SM8350 PCIe PIPE clks when disabled
- Add GDSCs to Qualcomm SC7280 LPASS audio clock controller
- Add missing XO clocks to Qualcomm MSM8226 and MSM8974
- Convert some Qualcomm clk DT bindings to YAML
- Reparenting fix for the clock supplying camera modules on Rockchip
rk3399
- Mark more critical (bus-)clocks on Rockchip rk3588"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (290 commits)
clk: qcom: gcc-sc8280xp: Add EMAC GDSCs
clk: starfive: Delete the redundant dev_set_drvdata() in JH7110 clock drivers
clk: rockchip: rk3588: make gate linked clocks critical
clk: qcom: dispcc-qcm2290: Remove inexistent DSI1PHY clk
clk: qcom: add the GPUCC driver for sa8775p
dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P
clk: qcom: gcc-sm8350: fix PCIe PIPE clocks handling
clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in lpass_cc_sc7280_desc
clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration
dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode property
clk: starfive: Avoid casting iomem pointers
clk: microchip: fix potential UAF in auxdev release callback
clk: qcom: rpm: Use managed `of_clk_add_hw_provider()`
clk: mediatek: fhctl: Mark local variables static
clk: sifive: make SiFive clk drivers depend on ARCH_ symbols
clk: uniphier: Use managed `of_clk_add_hw_provider()`
clk: si5351: Use managed `of_clk_add_hw_provider()`
clk: si570: Use managed `of_clk_add_hw_provider()`
clk: si514: Use managed `of_clk_add_hw_provider()`
clk: lmk04832: Use managed `of_clk_add_hw_provider()`
...

show more ...

Merge branch 'for-6.4/amd-sfh' into for-linus

- assorted functional fixes for amd-sfh driver (Basavaraj Natikar)

Merge branches 'clk-mediatek', 'clk-sunplus', 'clk-loongson' and 'clk-socfpga' into clk-next

- Frequency Hopping (FHCTL) on MediaTek MT6795, MT8173, MT8192 and
MT8195 SoCs
- Converted most Medi

Merge branches 'clk-mediatek', 'clk-sunplus', 'clk-loongson' and 'clk-socfpga' into clk-next

- Frequency Hopping (FHCTL) on MediaTek MT6795, MT8173, MT8192 and
MT8195 SoCs
- Converted most Mediatek clock drivers to struct platform_driver
- MediaTek clock drivers can be built as modules
- Mediatek MT8188 SoC clk drivers
- Clock driver for Sunplus SP7021 SoC
- Reimplement Loongson-1 clk driver with DT support
- Clk driver support for Loongson-2 SoCs
- Migrate socfpga clk driver to of_clk_add_hw_provider()

* clk-mediatek: (84 commits)
clk: mediatek: fhctl: Mark local variables static
clk: mediatek: Use right match table, include mod_devicetable
clk: mediatek: Add MT8188 adsp clock support
clk: mediatek: Add MT8188 imp i2c wrapper clock support
clk: mediatek: Add MT8188 wpesys clock support
clk: mediatek: Add MT8188 vppsys1 clock support
clk: mediatek: Add MT8188 vppsys0 clock support
clk: mediatek: Add MT8188 vencsys clock support
clk: mediatek: Add MT8188 vdosys1 clock support
clk: mediatek: Add MT8188 vdosys0 clock support
clk: mediatek: Add MT8188 vdecsys clock support
clk: mediatek: Add MT8188 mfgcfg clock support
clk: mediatek: Add MT8188 ipesys clock support
clk: mediatek: Add MT8188 imgsys clock support
clk: mediatek: Add MT8188 ccusys clock support
clk: mediatek: Add MT8188 camsys clock support
clk: mediatek: Add MT8188 infrastructure clock support
clk: mediatek: Add MT8188 peripheral clock support
clk: mediatek: Add MT8188 topckgen clock support
clk: mediatek: Add MT8188 apmixedsys clock support
...

* clk-sunplus:
clk: Add Sunplus SP7021 clock driver

* clk-loongson:
clk: clk-loongson2: add clock controller driver support
dt-bindings: clock: add loongson-2 boot clock index
MAINTAINERS: remove obsolete file entry in MIPS/LOONGSON1 ARCHITECTURE
MIPS: loongson32: Update the clock initialization
clk: loongson1: Re-implement the clock driver
clk: loongson1: Remove the outdated driver
dt-bindings: clock: Add Loongson-1 clock

* clk-socfpga:
clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
clk: socfpga: use of_clk_add_hw_provider and improve error handling
clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
clk: socfpga: use of_clk_add_hw_provider and improve error handling
clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
clk: socfpga: use of_clk_add_hw_provider and improve error handling

show more ...

Merge drm/drm-next into drm-intel-gt-next

Need to pull in commit from drm-next (earlier in drm-intel-next):

1eca0778f4b3 ("drm/i915: add struct i915_dsm to wrap dsm members together")

In order to

Merge drm/drm-next into drm-intel-gt-next

Need to pull in commit from drm-next (earlier in drm-intel-next):

1eca0778f4b3 ("drm/i915: add struct i915_dsm to wrap dsm members together")

In order to merge following patch to drm-intel-gt-next:

https://patchwork.freedesktop.org/patch/530942/?series=114925&rev=6

Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

show more ...

Merge drm/drm-next into drm-intel-next

Catch up with 6.3-rc cycle...

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Merge remote-tracking branch 'drm/drm-next' into msm-next

Merge drm-next into msm-next to pick up external clk and PM dependencies
for improved a6xx GPU reset sequence.

Signed-off-by: Rob Clark <ro

Merge remote-tracking branch 'drm/drm-next' into msm-next

Merge drm-next into msm-next to pick up external clk and PM dependencies
for improved a6xx GPU reset sequence.

Signed-off-by: Rob Clark <robdclark@chromium.org>

show more ...

Merge tag 'v6.3-rc2' into next

Merge with mainline to get of_property_present() and other newer APIs.

clk: mediatek: Add MODULE_DEVICE_TABLE() where appropriate

Add a MODULE_DEVICE_TABLE() on all clocks that can be built as modules
to allow auto-load at boot.

Signed-off-by: AngeloGioacchino Del Reg

clk: mediatek: Add MODULE_DEVICE_TABLE() where appropriate

Add a MODULE_DEVICE_TABLE() on all clocks that can be built as modules
to allow auto-load at boot.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Miles Chen <miles.chen@mediatek.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks
Link: https://lore.kernel.org/r/20230306140543.1813621-50-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

show more ...

clk: mediatek: Add MODULE_LICENSE() where missing

In order to successfully build clock drivers as modules it is required
to declare a module license: add it where missing.
While at it, also change t

clk: mediatek: Add MODULE_LICENSE() where missing

In order to successfully build clock drivers as modules it is required
to declare a module license: add it where missing.
While at it, also change the MODULE_LICENSE text from "GPL v2" to
"GPL" (which means the same) on clk-mt7981-eth.c.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Miles Chen <miles.chen@mediatek.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks
Link: https://lore.kernel.org/r/20230306140543.1813621-38-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

show more ...

clk: mediatek: Switch to module_platform_driver() where possible

Lots of clock drivers have got both .probe() and a .remove() callbacks:
switch from builtin_platform_driver() to module_platform_driv

clk: mediatek: Switch to module_platform_driver() where possible

Lots of clock drivers have got both .probe() and a .remove() callbacks:
switch from builtin_platform_driver() to module_platform_driver() so
that we actually register the .remove() callback.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Miles Chen <miles.chen@mediatek.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks
Link: https://lore.kernel.org/r/20230306140543.1813621-37-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

show more ...

clk: mediatek: Consistently use GATE_MTK() macro

All the various MediaTek clock drivers are, in a way or another,
redefining the GATE_MTK() macro with different names: while some
are doing that by a

clk: mediatek: Consistently use GATE_MTK() macro

All the various MediaTek clock drivers are, in a way or another,
redefining the GATE_MTK() macro with different names: while some
are doing that by actually using GATE_MTK(), others are copying
it entirely (hence, entirely redefining it).

Change all clock drivers to always and consistently use this macro.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks
Link: https://lore.kernel.org/r/20230306140543.1813621-23-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

show more ...

Merge drm/drm-fixes into drm-misc-fixes

Backmerging to get latest upstream.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>

Merge drm/drm-next into drm-misc-next

Backmerging to get v6.3-rc1 and sync with the other DRM trees.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>

Merge remote-tracking branch 'acme/perf-tools' into perf-tools-next

To pick up perf-tools fixes just merged upstream.

Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
"We have one small patch to the clk core this time around. It fixes a
corn

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
"We have one small patch to the clk core this time around. It fixes a
corner case with the CLK_OPS_PARENT_ENABLE flag combined with
clk_core_is_enabled() where it hangs the system. We'll simply assume
the clk is disabled if the parent is disabled and the flag is set.
Trying to turn on the parent to check the enable state of the clk runs
into system hangs at boot. We let this bake in -next for a couple
weeks to make sure there aren't any more issues because the last
attempt to fix this ran into hangs and had to be reverted.

Note: There were some more patches to the core framework around
sync_state and disabling unused clks, but I asked for that to be
reverted from the qcom PR because it isn't ready and we're still
discussing the best solution on the list.

Outside of the core clk framework, we have the usual collection of clk
driver updates and support for new SoCs (which seems to never stop).
The dirstat is dominated by Qualcomm because they added support for
quite a few SoCs this time around and also migrated quite a few of
their drivers to clk_parent_data. The other big diff is in the
Mediatek clk drivers that saw a significant rework this cycle to
similarly modernize the code, and we'll see that work continue in the
next cycle as well. Nothing really jumps out as scary here, except
that the significant churn in parent data descriptions can have typos
that go unnoticed. More details below.

Core:
- Honor CLK_OPS_PARENT_ENABLE in clk_core_is_enabled()

New Drivers:
- Add a new clk-gpr-mux clock type and use it on i.MX6Q to add ENET
ref clocks
- Support for Mediatek MT7891 SoC clks
- Support for many Qualcomm clk controllers:
- QDU1000/QRU1000 global clock controller
- SA8775P global clock controller
- SM8550 TCSR and display clock controller
- SM6350 clock controller
- MSM8996 CBF and APCS clock controllers

Updates:
- Various cleanups and improvements to Mediatek clk drivers to reduce
code size and modernize the drivers
- Support for Versa 5P49V60 clks
- Disable R-Car H3 ES1.*, as it was only available to an internal
development group and needed a lot of quirks and workarounds
- Add PWM, Compare-Match Timer (TIM), USB, SDHI, and eMMC clocks and
resets on Renesas RZ/V2M
- Add display clocks on Renesas R-Car V4H
- Add Camera Receiving Unit (CRU) clocks and resets on Renesas RZ/G2L
- Free the imx_uart_clocks even if imx_register_uart_clocks returns
early
- Get the stdout clocks count from device tree on i.MX
- Drop the clock count argument from imx_register_uart_clocks()
- Keep the uart clocks on i.MX93 for when earlycon is used
- Fix SPDX comment in i.MX6SLL clocks bindings header
- Drop some unnecessary spaces from i.MX8ULP clocks bindings header
- Add imx_obtain_fixed_of_clock() for allowing to add a clock that is
not configured via devicetree
- Fix the ENET1 gate configuration for i.MX6UL according to the
reference manual
- Add ENET refclock mux support for i.MX6UL
- Add support for USB host/device configuration on Renesas RZ/N1
- Add PLL2 programming support, and CAN-FD clocks on Renesas R-Car
V4H
- Add D1 CAN bus gates and resets for Allwinner
- Mark D1 CPUX clock as critical on Allwinner
- Reuse D1 driver for Allwinner R528/T113
- Cleanup sunxi-ng Kconfig
- Fix sunxi-ng kernel-doc issues
- Model Allwinner H3/H5 DRAM clock as fixed clock
- Use .determine_rate() instead of .round_rate() for the dualdiv,
mpll, sclk-div and cpu-dyn-div amlogic clock drivers
- DDR clocks were marked as critical in the proper clock driver for
each AT91 SoC such that drivers/memory/atmel-sdramc.c to be deleted
in the next releases as it only does clock enablement
- Patch to avoid compiling dt-compat.o for all AT91 SoCs as only some
of them may use it
- Support synchronous power_off requests in the qcom GDSC driver for
proper GPU power collapse
- Drop test clocks from various Qualcomm clk drivers
- Update parent references to use clk_parent_data/clk_hw in various
Qualcomm clk drivers
- Fixes for the Qualcomm MSM8996 CPU clock controller
- Transition Qualcomm MSM8974 GCC off the externally defined
sleep_clk
- Add GDSCs in the global clock controller for Qualcomm QCS404
- The SDCC core clocks on Qualcomm SM6115 are moved to floor_ops
- Programming of clk_dis_wait for GPU CX GDSC on Qualcomm SC7180 and
SDM845 are moved to use the recently introduced properties in the
GDSC struct
- Qualcomm's RPMh clock driver gains SM8550 and SA8775P clocks, and
the IPA clock is added on a variety of platforms
- De-duplicate identical clks in Qualcomm SMD RPM clk driver
- Add a few missing clocks across msm8998, msm8992, msm8916, qcs404
to Qualcomm SDM RPM clk driver
- Various Qualcomm clk drivers use devm_pm_runtime_enable() to
simplify"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (228 commits)
clk: qcom: apcs-msm8986: Include bitfield.h for FIELD_PREP
clk: qcom: Revert sync_state based clk_disable_unused
clk: imx: pll14xx: fix recalc_rate for negative kdiv
clk: rs9: Drop unused pin_xin field
MAINTAINERS: clk: imx: Add Peng Fan as reviewer
clk: sprd: Add dependency for SPRD_UMS512_CLK
clk: ralink: fix 'mt7621_gate_is_enabled()' function
clk: mediatek: clk-mtk: Remove unneeded semicolon
dt-bindings: clock: remove stih416 bindings
dt-bindings: clock: add loongson-2 clock
dt-bindings: clock: add loongson-2 clock include file
clk: imx: fix compile testing imxrt1050
clk: Honor CLK_OPS_PARENT_ENABLE in clk_core_is_enabled()
clk: imx: set imx_clk_gpr_mux_ops storage-class-specifier to static
clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*
dt-bindings: clock: Merge qcom,gpucc-sm8350 into qcom,gpucc.yaml
clk: qcom: gpucc-sdm845: fix clk_dis_wait being programmed for CX GDSC
clk: qcom: gpucc-sc7180: fix clk_dis_wait being programmed for CX GDSC
dt-bindings: clock: qcom,sa8775p-gcc: add the power-domains property
clk: qcom: cpu-8996: add missing cputype include
...

show more ...

Merge branches 'clk-microchip', 'clk-allwinner', 'clk-mediatek', 'clk-imx' and 'clk-core' into clk-next

- Various cleanups and improvements to Mediatek clk drivers to reduce
code size and modern

Merge branches 'clk-microchip', 'clk-allwinner', 'clk-mediatek', 'clk-imx' and 'clk-core' into clk-next

- Various cleanups and improvements to Mediatek clk drivers to reduce
code size and modernize the drivers
- Support for Mediatek MT7891 SoC clks

* clk-microchip:
clk: at91: do not compile dt-compat.c for sama7g5 and sam9x60
clk: at91: mark ddr clocks as critical

* clk-allwinner:
clk: sunxi-ng: d1: Add CAN bus gates and resets
dt-bindings: clock: Add D1 CAN bus gates and resets
clk: sunxi-ng: d1: Mark cpux clock as critical
clk: sunxi-ng: d1: Allow building for R528/T113
clk: sunxi-ng: Move SoC driver conditions to dependencies
clk: sunxi-ng: Remove duplicate ARCH_SUNXI dependencies
clk: sunxi-ng: Avoid computing the rate twice
clk: sunxi-ng: h3/h5: Model H3 CLK_DRAM as a fixed clock
clk: sunxi-ng: fix ccu_mmc_timing.c kernel-doc issues

* clk-mediatek: (29 commits)
clk: mediatek: clk-mtk: Remove unneeded semicolon
clk: mediatek: remove MT8195 vppsys/0/1 simple_probe
dt-bindings: arm: mediatek: migrate MT8195 vppsys0/1 to mtk-mmsys driver
clk: mediatek: add MT7981 clock support
dt-bindings: clock: mediatek: add mt7981 clock IDs
dt-bindings: clock: Add compatibles for MT7981
clk: mediatek: clk-mt7986-topckgen: Migrate to mtk_clk_simple_probe()
clk: mediatek: clk-mt7986-topckgen: Properly keep some clocks enabled
clk: mediatek: clk-mt6795-topckgen: Migrate to mtk_clk_simple_probe()
clk: mediatek: clk-mt8186-topckgen: Migrate to mtk_clk_simple_probe()
clk: mediatek: clk-mt8192: Migrate topckgen to mtk_clk_simple_probe()
clk: mediatek: clk-mtk: Register MFG notifier in mtk_clk_simple_probe()
clk: mediatek: clk-mt8183: Join top_aud_muxes and top_aud_divs
clk: mediatek: mt8186: Join top_adj_div and top_muxes
clk: mediatek: mt8192: Join top_adj_divs and top_muxes
clk: mediatek: clk-mt8192: Move CLK_TOP_CSW_F26M_D2 in top_divs
clk: mediatek: mt8173: Migrate pericfg/topckgen to mtk_clk_simple_probe()
clk: mediatek: clk-mtk: Extend mtk_clk_simple_probe()
clk: mediatek: Switch to mtk_clk_simple_probe() where possible
clk: mediatek: mt8173: Break down clock drivers and allow module build
...

* clk-imx:
clk: imx: pll14xx: fix recalc_rate for negative kdiv
MAINTAINERS: clk: imx: Add Peng Fan as reviewer
clk: imx: fix compile testing imxrt1050
clk: imx: set imx_clk_gpr_mux_ops storage-class-specifier to static
clk: imx6ul: add ethernet refclock mux support
clk: imx6ul: fix enet1 gate configuration
clk: imx: add imx_obtain_fixed_of_clock()
clk: imx6q: add ethernet refclock mux support
clk: imx: add clk-gpr-mux driver
dt-bindings: imx8ulp: clock: no spaces before tabs
clk: imx6sll: add proper spdx license identifier
clk: imx: imx93: invoke imx_register_uart_clocks
clk: imx: remove clk_count of imx_register_uart_clocks
clk: imx: get stdout clk count from device tree
clk: imx: avoid memory leak

* clk-core:
clk: Honor CLK_OPS_PARENT_ENABLE in clk_core_is_enabled()

show more ...

clk: mediatek: Switch to mtk_clk_simple_probe() where possible

mtk_clk_simple_probe() is a function that registers mtk gate clocks
and, if reset data is present, a reset controller and across all of

clk: mediatek: Switch to mtk_clk_simple_probe() where possible

mtk_clk_simple_probe() is a function that registers mtk gate clocks
and, if reset data is present, a reset controller and across all of
the MTK clock drivers, such a function is duplicated many times:
switch to the common mtk_clk_simple_probe() function for all of the
clock drivers that are registering as platform drivers.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Tested-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20230120092053.182923-12-angelogioacchino.delregno@collabora.com
Tested-by: Mingming Su <mingming.su@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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clk: mediatek: clk-gate: Propagate struct device with mtk_clk_register_gates()

Commit e4c23e19aa2a ("clk: mediatek: Register clock gate with device")
introduces a helper function for the sole purpos

clk: mediatek: clk-gate: Propagate struct device with mtk_clk_register_gates()

Commit e4c23e19aa2a ("clk: mediatek: Register clock gate with device")
introduces a helper function for the sole purpose of propagating a
struct device pointer to the clk API when registering the mtk-gate
clocks to take advantage of Runtime PM when/where needed and where
a power domain is defined in devicetree.

Function mtk_clk_register_gates() then becomes a wrapper around the
new mtk_clk_register_gates_with_dev() function that will simply pass
NULL as struct device: this is essential when registering drivers
with CLK_OF_DECLARE instead of as a platform device, as there will
be no struct device to pass... but we can as well simply have only
one function that always takes such pointer as a param and pass NULL
when unavoidable.

This commit removes the mtk_clk_register_gates() wrapper and renames
mtk_clk_register_gates_with_dev() to the former and all of the calls
to either of the two functions were fixed in all drivers in order to
reflect this change; also, to improve consistency with other kernel
functions, the pointer to struct device was moved as the first param.

Since a lot of MediaTek clock drivers are actually registering as a
platform device, but were still registering the mtk-gate clocks
without passing any struct device to the clock framework, they've
been changed to pass a valid one now, as to make all those platforms
able to use runtime power management where available.

While at it, some much needed indentation changes were also done.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com>
Tested-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20230120092053.182923-4-angelogioacchino.delregno@collabora.com
Tested-by: Mingming Su <mingming.su@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

show more ...

Merge branch 'main' into zstd-linus

Merge branch 'main' into zstd-next

Merge branch 'next' into for-linus

Prepare input updates for 6.1 merge window.

Merge branch 'for-6.1/logitech' into for-linus

- Add hanlding of all Bluetooth HID++ devices and fixes in hid++
(Bastien Nocera)