| 11350d2f | 09-Jun-2025 |
Inochi Amaoto <inochiama@gmail.com> |
riscv: dts: sophgo: sg2044: Add I2C device
The I2C controller of SG2044 is a standard Synopsys IP, with one
the ref clock is need.
Add I2C DT node for SG2044 SoC.
Link: https://lore.kernel.org/r/2
riscv: dts: sophgo: sg2044: Add I2C device
The I2C controller of SG2044 is a standard Synopsys IP, with one
the ref clock is need.
Add I2C DT node for SG2044 SoC.
Link: https://lore.kernel.org/r/20250608232836.784737-5-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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| cfb88696 | 09-Jun-2025 |
Inochi Amaoto <inochiama@gmail.com> |
riscv: dts: sophgo: sg2044: Add GPIO device
The GPIO controller is a standard Synopsys IP, which is already
supported by the kernel.
Add GPIO DT node for SG2044 SoC.
Link: https://lore.kernel.org/
riscv: dts: sophgo: sg2044: Add GPIO device
The GPIO controller is a standard Synopsys IP, which is already
supported by the kernel.
Add GPIO DT node for SG2044 SoC.
Link: https://lore.kernel.org/r/20250608232836.784737-4-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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| 1995b264 | 09-Jun-2025 |
Inochi Amaoto <inochiama@gmail.com> |
riscv: dts: sophgo: sg2044: Add clock controller device
Add clock controller and pll clock node for sg2044.
Link: https://lore.kernel.org/r/20250608232836.784737-3-inochiama@gmail.com
Signed-off-by
riscv: dts: sophgo: sg2044: Add clock controller device
Add clock controller and pll clock node for sg2044.
Link: https://lore.kernel.org/r/20250608232836.784737-3-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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| 95f119e3 | 09-Jun-2025 |
Inochi Amaoto <inochiama@gmail.com> |
riscv: dts: sophgo: sg2044: Add system controller device
The TOP system controller device is necessary for the SG2044 clock
controller. Add it to the SoC device tree.
Link: https://lore.kernel.org/
riscv: dts: sophgo: sg2044: Add system controller device
The TOP system controller device is necessary for the SG2044 clock
controller. Add it to the SoC device tree.
Link: https://lore.kernel.org/r/20250608232836.784737-2-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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| 108a7677 | 04-May-2025 |
Inochi Amaoto <inochiama@gmail.com> |
riscv: dts: sophgo: switch precise compatible for existed clock device for CV18XX
replace newly added precise compatible with old one for existed
clock device of CV18XX series SoCs.
Reviewed-by: Al
riscv: dts: sophgo: switch precise compatible for existed clock device for CV18XX
replace newly added precise compatible with old one for existed
clock device of CV18XX series SoCs.
Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Link: https://lore.kernel.org/r/20250504104553.1447819-4-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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| ae5bac37 | 14-Apr-2025 |
Inochi Amaoto <inochiama@gmail.com> |
riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10
Sophgo SG2044 SRD3-10 board bases on Sophgo SG2044 SoC.
This board includes 5 uart ports, 5 pcie x8 slots, 1 1G Ethernet port,
1 microSD
riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10
Sophgo SG2044 SRD3-10 board bases on Sophgo SG2044 SoC.
This board includes 5 uart ports, 5 pcie x8 slots, 1 1G Ethernet port,
1 microSD slot.
Add initial device tree of this board with uart support.
Link: https://lore.kernel.org/r/20250413223507.46480-11-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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| e595fa85 | 30-Apr-2025 |
Inochi Amaoto <inochiama@gmail.com> |
riscv: dts: sopgho: use SOC_PERIPHERAL_IRQ to calculate interrupt number
Since riscv and arm architecture use different interrupt definitions,
use a macro SOC_PERIPHERAL_IRQ mask this difference.
S
riscv: dts: sopgho: use SOC_PERIPHERAL_IRQ to calculate interrupt number
Since riscv and arm architecture use different interrupt definitions,
use a macro SOC_PERIPHERAL_IRQ mask this difference.
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Link: https://lore.kernel.org/r/20250430012654.235830-5-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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| a0cd6d17 | 30-Apr-2025 |
Inochi Amaoto <inochiama@gmail.com> |
riscv: dts: sophgo: rename header file cv18xx.dtsi to cv180x.dtsi
As the cv18xx.dtsi serves as a common peripheral header for all
riscv cv180x/cv181x/sg200x SoCs, it not cover the entire cv18xx
seri
riscv: dts: sophgo: rename header file cv18xx.dtsi to cv180x.dtsi
As the cv18xx.dtsi serves as a common peripheral header for all
riscv cv180x/cv181x/sg200x SoCs, it not cover the entire cv18xx
series as there is cv182x and cv183x. So rename the header file
to make it precise.
Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Link: https://lore.kernel.org/r/20250430012654.235830-4-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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| 0212bd4f | 30-Apr-2025 |
Inochi Amaoto <inochiama@gmail.com> |
riscv: dts: sophgo: Move riscv cpu definition to a separate file
As sg2000 and sg2002 can boot from an arm a53 core, it is not
suitable to left the riscv cpu definition in the common peripheral
head
riscv: dts: sophgo: Move riscv cpu definition to a separate file
As sg2000 and sg2002 can boot from an arm a53 core, it is not
suitable to left the riscv cpu definition in the common peripheral
header.
Move the riscv related device into a separate header file, so the
arm subsystem can reuse the common peripheral header.
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Link: https://lore.kernel.org/r/20250430012654.235830-3-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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| 33da812c | 30-Apr-2025 |
Inochi Amaoto <inochiama@gmail.com> |
riscv: dts: sophgo: Move all soc specific device into soc dtsi file
Although the cv1800b/cv1812h/sg2000/sg2002 share most peripherals,
some basic peripherals, like clock, pinctrl, clint and plint, a
riscv: dts: sophgo: Move all soc specific device into soc dtsi file
Although the cv1800b/cv1812h/sg2000/sg2002 share most peripherals,
some basic peripherals, like clock, pinctrl, clint and plint, are
not shared. These are caused by not only historical reason (plic,
clint), but also the fact the device is not the same (clock, pinctrl).
It is good to override device compatible when the SoC number is small,
but now it is a burden for maintenance, and it is kind of annoyed to
explain why using override. So it is time to move this out of the
common peripheral header.
Move all soc related peripheral device from common peripheral header
to the soc specific header to get rid of most compatible override.
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Link: https://lore.kernel.org/r/20250430012654.235830-2-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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| 73ab31a8 | 25-Apr-2025 |
Zixian Zeng <sycamoremoon376@gmail.com> |
riscv: sophgo: dts: Add spi controller for SG2042
Add spi controllers for SG2042.
SG2042 uses the upstreamed Synopsys DW SPI IP.
Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
Link: https:
riscv: sophgo: dts: Add spi controller for SG2042
Add spi controllers for SG2042.
SG2042 uses the upstreamed Synopsys DW SPI IP.
Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
Link: https://lore.kernel.org/r/20250425-sfg-spi-v6-3-2dbe7bb46013@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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| f047a928 | 12-Feb-2025 |
Chen Wang <unicorn_wang@outlook.com> |
riscv: sophgo: dts: add cooling maps for Milk-V Pioneer
The normal operating temperature range of SG2042 is -20 degrees
Celsius ~ 85 degrees Celsius.
Simultaneously monitor soc temperature and boar
riscv: sophgo: dts: add cooling maps for Milk-V Pioneer
The normal operating temperature range of SG2042 is -20 degrees
Celsius ~ 85 degrees Celsius.
Simultaneously monitor soc temperature and board temperature to
improve redundancy and safety.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/5a36a2784d97ed7b1e06777cb0c3c14fe9185e99.1739351437.git.unicorn_wang@outlook.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
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| 62cdf0a0 | 12-Feb-2025 |
Chen Wang <unicorn_wang@outlook.com> |
riscv: sophgo: dts: add pwm-fan for Milk-V Pioneer
Milk-V Pioneer uses fan as cooling-device, and speed of the fan is
controlled by the first channel of pwm controller of SG2042.
Signed-off-by: Che
riscv: sophgo: dts: add pwm-fan for Milk-V Pioneer
Milk-V Pioneer uses fan as cooling-device, and speed of the fan is
controlled by the first channel of pwm controller of SG2042.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/dd23362328f77dd91aa9354848bbb0abad0f554b.1739351437.git.unicorn_wang@outlook.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
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| b5cf65cc | 25-Oct-2024 |
Inochi Amaoto <inochiama@outlook.com> |
riscv: dts: sophgo: Add emmc support for Huashan Pi
Add emmc node configuration for Huashan Pi.
Link: https://lore.kernel.org/r/20241025112902.1200716-3-inochiama@gmail.com
Signed-off-by: Inochi Am
riscv: dts: sophgo: Add emmc support for Huashan Pi
Add emmc node configuration for Huashan Pi.
Link: https://lore.kernel.org/r/20241025112902.1200716-3-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
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| 06133f48 | 25-Oct-2024 |
Inochi Amaoto <inochiama@gmail.com> |
riscv: dts: sophgo: Add sdio configuration for Huashan Pi
Add configuration for sdio for Huashan Pi to support sdio wifi.
Link: https://lore.kernel.org/r/20241025112902.1200716-2-inochiama@gmail.co
riscv: dts: sophgo: Add sdio configuration for Huashan Pi
Add configuration for sdio for Huashan Pi to support sdio wifi.
Link: https://lore.kernel.org/r/20241025112902.1200716-2-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
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| 44196383 | 28-Oct-2024 |
Thomas Bonnefille <thomas.bonnefille@bootlin.com> |
riscv: dts: sophgo: fix pinctrl base-address
Fix the base-address of the pinctrl controller to match its register
address.
Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Reviewed-
riscv: dts: sophgo: fix pinctrl base-address
Fix the base-address of the pinctrl controller to match its register
address.
Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Reviewed-by: Inochi Amaoto <inochiama@gmail.com>
Fixes: 93b61555f509 ("riscv: dts: sophgo: Add initial SG2002 SoC device tree")
Link: https://lore.kernel.org/r/20241028-fix-address-v1-1-dcbe21e59ccf@bootlin.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
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| 128bded4 | 08-Oct-2024 |
Chen Wang <unicorn_wang@outlook.com> |
riscv: sophgo: dts: add power key for pioneer box
There is a power button on the front panel of the pioneer box.
Short pressing the button will trigger the onboard MCU to
notify SG2042 through GPIO2
riscv: sophgo: dts: add power key for pioneer box
There is a power button on the front panel of the pioneer box.
Short pressing the button will trigger the onboard MCU to
notify SG2042 through GPIO22 to enter the power-off process.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/12e65a99f1b52c52b7372e900a203063b30c74b5.1728350655.git.unicorn_wang@outlook.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
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