| e3ba31b7 | 06-Apr-2022 |
Christophe Leroy <christophe.leroy@csgroup.eu> |
powerpc/8xx: Remove mpc8xx_pics_init()
mpc8xx_pics_init() is now only a trampoline to
mpc8xx_pic_init().
Remove mpc8xx_pics_init() and use mpc8xx_pic_init()
directly.
Signed-off-by: Christophe Ler
powerpc/8xx: Remove mpc8xx_pics_init()
mpc8xx_pics_init() is now only a trampoline to
mpc8xx_pic_init().
Remove mpc8xx_pics_init() and use mpc8xx_pic_init()
directly.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/9c55a698adb5ba3b7b77023170fcaf0acb5d2d81.1649226186.git.christophe.leroy@csgroup.eu
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| 14d893fc | 06-Apr-2022 |
Christophe Leroy <christophe.leroy@csgroup.eu> |
powerpc/8xx: Convert CPM1 interrupt controller to platform_device
In the same logic as commit be7ecbd240b2 ("soc: fsl: qe: convert QE
interrupt controller to platform_device"), convert CPM1 interrup
powerpc/8xx: Convert CPM1 interrupt controller to platform_device
In the same logic as commit be7ecbd240b2 ("soc: fsl: qe: convert QE
interrupt controller to platform_device"), convert CPM1 interrupt
controller to platform_device.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/fb80d0b2077312079c49da0296e25591578771cd.1649226186.git.christophe.leroy@csgroup.eu
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| 22add2a2 | 06-Apr-2022 |
Christophe Leroy <christophe.leroy@csgroup.eu> |
powerpc/8xx: Convert CPM1 error interrupt handler to platform driver
Add CPM error interrupt as a standalone platform driver,
to simplify the init of CPM interrupt handler.
Signed-off-by: Christoph
powerpc/8xx: Convert CPM1 error interrupt handler to platform driver
Add CPM error interrupt as a standalone platform driver,
to simplify the init of CPM interrupt handler.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/375a72df6e4a26c5959cc81a6c6d46152efa2306.1649226186.git.christophe.leroy@csgroup.eu
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| bccc5898 | 24-Nov-2020 |
Christophe Leroy <christophe.leroy@csgroup.eu> |
powerpc/8xx: Always pin kernel text TLB
There is no big poing in not pinning kernel text anymore, as now
we can keep pinned TLB even with things like DEBUG_PAGEALLOC.
Remove CONFIG_PIN_TLB_TEXT, ma
powerpc/8xx: Always pin kernel text TLB
There is no big poing in not pinning kernel text anymore, as now
we can keep pinned TLB even with things like DEBUG_PAGEALLOC.
Remove CONFIG_PIN_TLB_TEXT, making it always right.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
[mpe: Drop ifdef around mmu_pin_tlb() to fix build errors]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/203b89de491e1379f1677a2685211b7c32adfff0.1606231483.git.christophe.leroy@csgroup.eu
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| fcdafd10 | 19-May-2020 |
Christophe Leroy <christophe.leroy@csgroup.eu> |
powerpc/8xx: Allow large TLBs with DEBUG_PAGEALLOC
DEBUG_PAGEALLOC only manages RW data.
Text and RO data can still be mapped with hugepages and pinned TLB.
In order to map with hugepages, also en
powerpc/8xx: Allow large TLBs with DEBUG_PAGEALLOC
DEBUG_PAGEALLOC only manages RW data.
Text and RO data can still be mapped with hugepages and pinned TLB.
In order to map with hugepages, also enforce a 512kB data alignment
minimum. That's a trade-off between size of speed, taking into
account that DEBUG_PAGEALLOC is a debug option. Anyway the alignment
is still tunable.
We also allow tuning of alignment for book3s to limit the complexity
of the test in Kconfig that will anyway disappear in the following
patches once DEBUG_PAGEALLOC is handled together with BATs.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/c13256f2d356a316715da61fe089b3623ef217a5.1589866984.git.christophe.leroy@csgroup.eu
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| da1adea0 | 19-May-2020 |
Christophe Leroy <christophe.leroy@csgroup.eu> |
powerpc/8xx: Allow STRICT_KERNEL_RwX with pinned TLB
Pinned TLB are 8M. Now that there is no strict boundary anymore
between text and RO data, it is possible to use 8M pinned executable
TLB that cov
powerpc/8xx: Allow STRICT_KERNEL_RwX with pinned TLB
Pinned TLB are 8M. Now that there is no strict boundary anymore
between text and RO data, it is possible to use 8M pinned executable
TLB that covers both text and RO data.
When PIN_TLB_DATA or PIN_TLB_TEXT is selected, enforce 8M RW data
alignment and allow STRICT_KERNEL_RWX.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/c535fc97bf0dd8693192e25feeed8088701e00c6.1589866984.git.christophe.leroy@csgroup.eu
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| 136a9a0f | 19-May-2020 |
Christophe Leroy <christophe.leroy@csgroup.eu> |
powerpc/8xx: Don't set IMMR map anymore at boot
Only early debug requires IMMR to be mapped early.
No need to set it up and pin it in assembly. Map it
through page tables at udbg init when necessar
powerpc/8xx: Don't set IMMR map anymore at boot
Only early debug requires IMMR to be mapped early.
No need to set it up and pin it in assembly. Map it
through page tables at udbg init when necessary.
If CONFIG_PIN_TLB_IMMR is selected, pin it once we
don't need the 32 Mb pinned RAM anymore.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/13c1e8539fdf363d3146f4884e5c3c76c6c308b5.1589866984.git.christophe.leroy@csgroup.eu
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| 5d465669 | 19-May-2020 |
Christophe Leroy <christophe.leroy@csgroup.eu> |
powerpc/8xx: Move PPC_PIN_TLB options into 8xx Kconfig
PPC_PIN_TLB options are dedicated to the 8xx, move them into
the 8xx Kconfig.
While we are at it, add some text to explain what it does.
Sign
powerpc/8xx: Move PPC_PIN_TLB options into 8xx Kconfig
PPC_PIN_TLB options are dedicated to the 8xx, move them into
the 8xx Kconfig.
While we are at it, add some text to explain what it does.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/1ece39fac6312e1d14e6a67b3f9d9f9f91990a7b.1589866984.git.christophe.leroy@csgroup.eu
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| eafd687e | 12-Sep-2019 |
Christophe Leroy <christophe.leroy@c-s.fr> |
powerpc/8xx: use the fixmapped IMMR in cpm_reset()
Since commit f86ef74ed919 ("powerpc/8xx: Fix vaddr for IMMR early
remap"), the IMMR area has been mapped at startup with fixmap.
Use that fixmap d
powerpc/8xx: use the fixmapped IMMR in cpm_reset()
Since commit f86ef74ed919 ("powerpc/8xx: Fix vaddr for IMMR early
remap"), the IMMR area has been mapped at startup with fixmap.
Use that fixmap directly instead of calling ioremap(), this
avoids calling ioremap() early before the slab is available.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/f816ccdbd15b97cf43c5a8c7cc8dfa8db58ff036.1568294935.git.christophe.leroy@c-s.fr
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| 43db76f4 | 14-Jun-2019 |
Christophe Leroy <christophe.leroy@c-s.fr> |
powerpc/8xx: Add microcode patch to move SMC parameter RAM.
Some SCC functions like the QMC requires an extended parameter RAM.
On modern 8xx (ie 866 and 885), SPI area can already be relocated,
all
powerpc/8xx: Add microcode patch to move SMC parameter RAM.
Some SCC functions like the QMC requires an extended parameter RAM.
On modern 8xx (ie 866 and 885), SPI area can already be relocated,
allowing the use of those functions on SCC2. But SCC3 and SCC4
parameter RAM collide with SMC1 and SMC2 parameter RAMs.
This patch adds microcode to allow the relocation of both SMC1 and
SMC2, and relocate them at offsets 0x1ec0 and 0x1fc0.
Those offsets are by default for the CPM1 DSP1 and DSP2, but there
is no kernel driver using them at the moment so this area can be
reused.
This microcode is provided by Freescale/NXP in Engineering Bulletin
EB662 ("MPC8xx I2C/SPI and SMC Relocation Microcode Packages")
dated 2006. The binary code is public. The source is not available.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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| c3eec5d7 | 14-Jun-2019 |
Christophe Leroy <christophe.leroy@c-s.fr> |
powerpc/8xx: Use IO accessors in microcode programming.
Change microcode functions to use IO accessors and get rid
of volatile attributes.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
powerpc/8xx: Use IO accessors in microcode programming.
Change microcode functions to use IO accessors and get rid
of volatile attributes.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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| 647d5ed0 | 14-Jun-2019 |
Christophe Leroy <christophe.leroy@c-s.fr> |
powerpc/8xx: replace #ifdefs by IS_ENABLED() in microcode.c
Reduce #ifdef mess by using IS_ENABLED() instead.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerm
powerpc/8xx: replace #ifdefs by IS_ENABLED() in microcode.c
Reduce #ifdef mess by using IS_ENABLED() instead.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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| f5348c08 | 14-Jun-2019 |
Christophe Leroy <christophe.leroy@c-s.fr> |
powerpc/8xx: refactor programming of microcode CPM params.
The CPM registers RCCR and CPMCR1..4 registers has to be set in
accordance with the microcode patch beeing programmed. Lets
define them as
powerpc/8xx: refactor programming of microcode CPM params.
The CPM registers RCCR and CPMCR1..4 registers has to be set in
accordance with the microcode patch beeing programmed. Lets
define them as part of the patch set and refactor their
programming from that definition.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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