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Revision tags: release/14.0.0 |
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95ee2897 |
| 16-Aug-2023 |
Warner Losh <imp@FreeBSD.org> |
sys: Remove $FreeBSD$: two-line .h pattern
Remove /^\s*\*\n \*\s+\$FreeBSD\$$\n/
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Revision tags: release/13.2.0, release/12.4.0, release/13.1.0, release/12.3.0, release/13.0.0, release/12.2.0, release/11.4.0 |
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59abbffa |
| 31-Jan-2020 |
Dimitry Andric <dim@FreeBSD.org> |
Merge ^/head r357270 through r357349.
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03178616 |
| 30-Jan-2020 |
John Baldwin <jhb@FreeBSD.org> |
Remove unused fields from struct pcb.
cpu_switch/throw() and savectx() do not save or restore any values in
these fields which mostly held non-callee-save registers.
makectx() copied these fields f
Remove unused fields from struct pcb.
cpu_switch/throw() and savectx() do not save or restore any values in
these fields which mostly held non-callee-save registers.
makectx() copied these fields from kdb_frame, but they weren't used
except for PC_REGS using pcb_sepc. Change PC_REGS to use
kdb_frame->tf_sepc directly instead.
Reviewed by: br
MFC after: 2 weeks
Sponsored by: DARPA
Differential Revision: https://reviews.freebsd.org/D23395
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Revision tags: release/12.1.0, release/11.3.0 |
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30e009fc |
| 19-Feb-2019 |
Enji Cooper <ngie@FreeBSD.org> |
MFhead@r344270
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c981cbbd |
| 15-Feb-2019 |
Dimitry Andric <dim@FreeBSD.org> |
Merge ^/head r343956 through r344177.
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35c91b0c |
| 13-Feb-2019 |
Mark Johnston <markj@FreeBSD.org> |
Implement per-CPU pmap activation tracking for RISC-V.
This reduces the overhead of TLB invalidations by ensuring that we
only interrupt CPUs which are using the given pmap. Tracking is
performed i
Implement per-CPU pmap activation tracking for RISC-V.
This reduces the overhead of TLB invalidations by ensuring that we
only interrupt CPUs which are using the given pmap. Tracking is
performed in pmap_activate(), which gets called during context switches:
from cpu_throw(), if a thread is exiting or an AP is starting, or
cpu_switch() for a regular context switch.
For now, pmap_sync_icache() still must interrupt all CPUs.
Reviewed by: kib (earlier version), jhb
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D18874
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Revision tags: release/12.0.0, release/11.2.0, release/10.4.0, release/11.1.0 |
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67bc8c8b |
| 19-Nov-2016 |
Dimitry Andric <dim@FreeBSD.org> |
Merge ^/head r308491 through r308841.
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7804dd52 |
| 16-Nov-2016 |
Ruslan Bukin <br@FreeBSD.org> |
Add full softfloat and hardfloat support for RISC-V.
Hardfloat is now default (use riscv64sf as TARGET_ARCH
for softfloat).
Sponsored by: DARPA, AFRL
Differential Revision: https://reviews.freebsd.
Add full softfloat and hardfloat support for RISC-V.
Hardfloat is now default (use riscv64sf as TARGET_ARCH
for softfloat).
Sponsored by: DARPA, AFRL
Differential Revision: https://reviews.freebsd.org/D8529
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Revision tags: release/11.0.1, release/11.0.0, release/10.3.0 |
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b626f5a7 |
| 04-Jan-2016 |
Glen Barber <gjb@FreeBSD.org> |
MFH r289384-r293170
Sponsored by: The FreeBSD Foundation
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9a7cd2e6 |
| 22-Dec-2015 |
Bjoern A. Zeeb <bz@FreeBSD.org> |
MFH @r292599
This includes the pluggable TCP framework and other chnages to the
netstack to track for VNET stability.
Security: The FreeBSD Foundation
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8d7e7a98 |
| 17-Dec-2015 |
Ruslan Bukin <br@FreeBSD.org> |
Import RISC-V machine headers. This is a minimal set required to compile
kernel and userland.
Reviewed by: andrew, imp, kib
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
Differential Revision: https
Import RISC-V machine headers. This is a minimal set required to compile
kernel and userland.
Reviewed by: andrew, imp, kib
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
Differential Revision: https://reviews.freebsd.org/D4554
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