ig4(4): Add an EMAG device type

Sponsored by: Ampere Computing LLC, Netflix
Submitted by: allanjude
Differential Revision: https://reviews.freebsd.org/D28746
Reviewed by: imp

sys: Remove $FreeBSD$: two-line .h pattern

Remove /^\s*\*\n \*\s+\$FreeBSD\$$\n/

ichiic: use bool for one-bit wide bit-fields

A one-bit wide bit-field can take only the values 0 and -1. Clang 16
introduced a warning that "implicit truncation from 'int' to a one-bit
wide bit-fiel

ichiic: use bool for one-bit wide bit-fields

A one-bit wide bit-field can take only the values 0 and -1. Clang 16
introduced a warning that "implicit truncation from 'int' to a one-bit
wide bit-field changes value from 1 to -1". Fix by using c99 bool.

Reported by: Clang
Reviewed by: emaste, wulf
MFC after: 3 days
Differential Revision: https://reviews.freebsd.org/D39665

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ichiic: Remove unused devclass arguments to DRIVER_MODULE.

ig4: Add PCI IDs for Intel Gemini Lake I2C controller.

Submitted by: Dmitry Luhtionov
MFC after: 2 weeks

ig4(4): Add PCI IDs for Intel Tiger Lake

Submitted by: Neel Chauhan <neel AT neelc DOT org>
Differential Revision: https://reviews.freebsd.org/D27483

[ig4] Enable additional registers support on Appolo Lake controllers

To be inline with intel-lpss Linux driver

[ig4] Add support for CannonLake controllers

They are clocked at 216MHz rate, much higher than previous models.

PR: 240485
Submitted by: Neel Chauhan <neel@neelc.org>

[ig4] Remove dead code inherited from DragonflyBSD

[ig4] Add suspend/resume support

That is done with re-execution of controller initialization procedure
from resume handler.

PR: 238037

[ig4] Implement burst mode for data reads

In this mode DATA_CMD register reads and writes are performed in
TX/RX FIFO-sized bursts to increase I2C bus utilization.

That reduces read time from 60us

[ig4] Implement burst mode for data reads

In this mode DATA_CMD register reads and writes are performed in
TX/RX FIFO-sized bursts to increase I2C bus utilization.

That reduces read time from 60us to 30us per byte when read data is fit
in to RX FIFO buffer in FAST speed mode in my setup.

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[ig4] Set clock registers based on controller model

IC clock rates are varied between different controller models so we have
to adjust timing registers in each case individually. Borrow intresting
c

[ig4] Set clock registers based on controller model

IC clock rates are varied between different controller models so we have
to adjust timing registers in each case individually. Borrow intresting
constants and formulas from Intel specs, i2c-designware and lpss_intel
drivers and apply them to FreeBSD supported controller models.

Implement fetching of timing data via ACPI methods execution if available.

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[ig4] Do not wait until interrupts are enabled at attach stage

as the driver is fully functional on a cold boot through utilization of
polled mode.

As a side effect, ig4 children probe and attach m

[ig4] Do not wait until interrupts are enabled at attach stage

as the driver is fully functional on a cold boot through utilization of
polled mode.

As a side effect, ig4 children probe and attach methods can be called
earlier in the boot sequence, so now it is up to the child drivers
to wait for a kernel initialization completion if it is required.

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[ig4] Allow enabling of polled mode from iicbus allocation callback

If controller is allocated with IIC_NOWAIT option ig4 enables polled mode
for a period of allocation that makes possible to start

[ig4] Allow enabling of polled mode from iicbus allocation callback

If controller is allocated with IIC_NOWAIT option ig4 enables polled mode
for a period of allocation that makes possible to start I2C transfers
from the contexts where sleeping is not allowed e.g. from ithreads or
callouts.

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[ig4] Reduce scope of io_lock

Now io_lock is used as condition variable to synchronize active process with
the interrupt handler. It is not used for tasks other than waiting for
interrupt and passin

[ig4] Reduce scope of io_lock

Now io_lock is used as condition variable to synchronize active process with
the interrupt handler. It is not used for tasks other than waiting for
interrupt and passing parameters to and from it's handler.

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[ig4] Drop driver's internal RX FIFO

There is no need to read all controller's RX FIFO data to clear RX_FULL
bit in interrupt handler as interrupts are masked permanently since
previous commit.

[ig4] Only enable interrupts when we want them. Otherwise keep mask at 0.

This avoids possible interrupt storms, depending on the state of the I2C
controller before the driver attached.

During atta

[ig4] Only enable interrupts when we want them. Otherwise keep mask at 0.

This avoids possible interrupt storms, depending on the state of the I2C
controller before the driver attached.

During attaching this clears the interrupt mask.

Revert r338215 as this change makes it no-op.

Obtained from: DragonflyBSD (d7c8555)

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[ig4] Give common name to PCI and ACPI device drivers

They share common device driver code with different bus attachments

This commit starts a bunch of changes which have following properties:

Rev

[ig4] Give common name to PCI and ACPI device drivers

They share common device driver code with different bus attachments

This commit starts a bunch of changes which have following properties:

Reviewed by: imp (previous version)
MFC after: 1 month
Differential Revision: https://reviews.freebsd.org/D22016

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Merge ^/head r338026 through r338297, and resolve conflicts.

[ig4] Fix I/O timeout issue with Designware I2C controller on AMD platforms

Due to hardware limitation AMD I2C controller can't trigger pending
interrupt if interrupt status has been changed after c

[ig4] Fix I/O timeout issue with Designware I2C controller on AMD platforms

Due to hardware limitation AMD I2C controller can't trigger pending
interrupt if interrupt status has been changed after clearing
interrupt status bits. So, I2C will lose the interrupt and IO will be
timed out. Implements a workaround to disable I2C controller interrupt
and re-enable I2C interrupt before existing interrupt handler.

Submitted by: rajfbsd@gmail.com
MFC after: 2 weeks
Differential Revision: https://reviews.freebsd.org/D16720

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ig4(4): add support for Apollo Lake I2C controllers

Add PCI ids for I2C controllers on Apollo Lake platform. Also convert
switch/case probe logic into a table.

Reviewed by: avg
Differential Revisio

ig4(4): add support for Apollo Lake I2C controllers

Add PCI ids for I2C controllers on Apollo Lake platform. Also convert
switch/case probe logic into a table.

Reviewed by: avg
Differential Revision: https://reviews.freebsd.org/D16120

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[ig4] Add support for i2c controllers on Skylake and Kaby Lake

This was tested by Ben on HP Chromebook 13 G1 with a
Skylake CPU and Sunrise Point-LP I2C controller and by me on
Minnowboard Turbot w

[ig4] Add support for i2c controllers on Skylake and Kaby Lake

This was tested by Ben on HP Chromebook 13 G1 with a
Skylake CPU and Sunrise Point-LP I2C controller and by me on
Minnowboard Turbot with Atom E3826 (formerly Bay Trail)

Submitted by: Ben Pye <ben@curlybracket.co.uk>
Reviewed by: gonzo
Obtained from: DragonflyBSD (a4549657 by Imre Vadász)
MFC after: 2 weeks
Differential Revision: https://reviews.freebsd.org/D13654

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[ig4] Add ACPI platform support for ig4 driver

Add ACPI part for ig4 driver to make it work on Intel BayTrail SoC where
ig4 device is available only through ACPI

Reviewed by: avg
MFC after: 1 week

[ig4] Add ACPI platform support for ig4 driver

Add ACPI part for ig4 driver to make it work on Intel BayTrail SoC where
ig4 device is available only through ACPI

Reviewed by: avg
MFC after: 1 week
Differential Revision: https://reviews.freebsd.org/D8742

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Merge ^/head r303250 through r308226.

ichiic/ig4: completely disengage from smbus

MFC after: 5 weeks