Merge head from 7/28

MFC @ r266724

An SVM update will follow this.

Add missing Ivy Bridge and Haswell events.

Submitted by: Anton Rang <rang@mac.com>
MFC: 2 weeks

Merge head

IFC @264767

Merge head up to r263906.

Update hwpmc to support core events for Atom Silvermont microarchitecture.
(Model 0x4D as per Intel document 330061-001 01/2014)

Tested by: Olivier Cochard-Labbe <olivier@cochatrd.me>
MFC after: 4 w

Update hwpmc to support core events for Atom Silvermont microarchitecture.
(Model 0x4D as per Intel document 330061-001 01/2014)

Tested by: Olivier Cochard-Labbe <olivier@cochatrd.me>
MFC after: 4 weeks

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MFH: tracking commit

Sponsored by: The FreeBSD Foundation

Merge head up to r262222 (last merge was incomplete).

Add hwpmc(4) support for the PowerPC 970 class processors, direct events.
This also fixes asserts on removal of the module for the mpc74xx.

The PowerPC 970 processors have two different types of eve

Add hwpmc(4) support for the PowerPC 970 class processors, direct events.
This also fixes asserts on removal of the module for the mpc74xx.

The PowerPC 970 processors have two different types of events: direct events
and indirect events. Thus far only direct events are supported. I included
some documentation in the driver on how indirect events work, but support is
for the future.

MFC after: 1 month

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Merge head r233826 through r256722.

IFC @256277

Approved by: ken (mentor)

IFC @ r255692

Comment out IA32_MISC_ENABLE MSR access - this doesn't exist on AMD.
Need to sort out how arch-specific MSRs will be handled.

Merge from head

IFC @ r255209

MFC

Remove the duplicate LLC_MISS event and put it in the right order.

MFC

Update the mis-predicted branch PMC names (for sandy bridge) to not clash.

The SDM (June 2013) tables on these are rather confusing. Yes, they
assign the same name (BR_MISP_RETIRED.ALL_BRANCHES) to

Update the mis-predicted branch PMC names (for sandy bridge) to not clash.

The SDM (June 2013) tables on these are rather confusing. Yes, they
assign the same name (BR_MISP_RETIRED.ALL_BRANCHES) to two codes
(C5H/00H and C5H/04H.) The latter however is the PEBS version.

So, to make it easier to see the difference - and yes, we can use
both without having to actually enable the PEBS specific bits! -
just rename the PEBS one to _PS so there's no clashing.

Tested:

* Sandy bridge

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MFC

Update the MEM_UOP_RETIRED PMC operation for sandy bridge and sandy
bridge Xeon.

Summary: These are PEBS events but they're also available as normal
counter/sample events. The source table (Table 1

Update the MEM_UOP_RETIRED PMC operation for sandy bridge and sandy
bridge Xeon.

Summary: These are PEBS events but they're also available as normal
counter/sample events. The source table (Table 19-2) lists the
base versions (LOAD, STLB_MISS, SPLIT, ALL) but it says they must
be qualified with other values. This particular commit fleshes
out those umask values.

Source:

* Linux; SDM June 2013, Volume 3B, Table 19-2 and 18-21.

Tested:

* Sandy Bridge (non-Xeon)

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IFC.

Change the name of this particular event to reflect the name used in
Linux and Intel examples.

Sourced:

* https://github.com/andikleen/pmu-tools/blob/master/snb-client.csv
* http://software.intel.c

Change the name of this particular event to reflect the name used in
Linux and Intel examples.

Sourced:

* https://github.com/andikleen/pmu-tools/blob/master/snb-client.csv
* http://software.intel.com/en-us/comment/1747932#comment-1747932

Note:

* It's not currently in the Intel SDM; I need to chase down what's
going on.

Tested:

* Sandy Bridge

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Correct a typo in the event mask mnemonic.

Reviewed by: gnn
MFC after: 3 days

Add in missing events for Sandy Bridge Xeon.

* Add in MEM_LOAD_UOPS_LLC_HIT_RETIRED for both sandy bridge and sandy
bridge Xeon. Right now it only is enabled for Sandy Bridge.
* D2/0F is actually

Add in missing events for Sandy Bridge Xeon.

* Add in MEM_LOAD_UOPS_LLC_HIT_RETIRED for both sandy bridge and sandy
bridge Xeon. Right now it only is enabled for Sandy Bridge.
* D2/0F is actually a combination rather than a separate counter, so
just flip that on for the CPU types that support it.

There's an errata for using this on SB Xeon hardware - I've documented
it in kern/181346.

Tested:

* Sandy Bridge
* Sandy Bridge Xeon

Sponsored by: Netflix, Inc.

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