riscv: Allwinner D1 clock and reset driver

Add the SOC_ALLWINNER_D1 config option, following other platforms.

Co-authored-by: mhorne
Reviewed by: manu (previous version)
Sponsored by: The FreeBSD F

riscv: Allwinner D1 clock and reset driver

Add the SOC_ALLWINNER_D1 config option, following other platforms.

Co-authored-by: mhorne
Reviewed by: manu (previous version)
Sponsored by: The FreeBSD Foundation (in part)
Differential Revision: https://reviews.freebsd.org/D47515

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riscv: support PV_STATS pmap option

It is rarely used but trivially supported; add the missing stat calls
and enable it in LINT.

Reviewed by: markj, br (previous version), jhb (previous version)
Sp

riscv: support PV_STATS pmap option

It is rarely used but trivially supported; add the missing stat calls
and enable it in LINT.

Reviewed by: markj, br (previous version), jhb (previous version)
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D45475

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sys: Remove $FreeBSD$: one-line sh pattern

Remove /^\s*#[#!]?\s*\$FreeBSD\$.*$\n/

riscv: retire the FPE kernel option

We always build the kernel floating point support. Now that the
riscv64sf userspace variant has been removed the option is required for
correct operation.

Review

riscv: retire the FPE kernel option

We always build the kernel floating point support. Now that the
riscv64sf userspace variant has been removed the option is required for
correct operation.

Reviewed by: jhb
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D39851

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conf: Document why we have ARM64 and RISCV options

These are needed for the 'cpu ARM64' and 'cpu RISCV' options in these
architecture's config files. cpu lines are non-optional in config(8), so
we m

conf: Document why we have ARM64 and RISCV options

These are needed for the 'cpu ARM64' and 'cpu RISCV' options in these
architecture's config files. cpu lines are non-optional in config(8), so
we must define them here. There's no other use for them in the tree.

Sponsored by: Netflix

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o Add driver for PLIC (Platform-Level Interrupt Controller) device.
o Convert interrupt machdep support to use INTRNG code.

Sponsored by: DARPA, AFRL

Merge ^/head r308491 through r308841.

Add full softfloat and hardfloat support for RISC-V.

Hardfloat is now default (use riscv64sf as TARGET_ARCH
for softfloat).

Sponsored by: DARPA, AFRL
Differential Revision: https://reviews.freebsd.

Add full softfloat and hardfloat support for RISC-V.

Hardfloat is now default (use riscv64sf as TARGET_ARCH
for softfloat).

Sponsored by: DARPA, AFRL
Differential Revision: https://reviews.freebsd.org/D8529

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Revert r298477 ("Clear the DDR memory").

There is no need to clear all the DDR memory (we only need to clear
BSS section).
I was playing with non-default version of hardware (the bitfile
synthesized

Revert r298477 ("Clear the DDR memory").

There is no need to clear all the DDR memory (we only need to clear
BSS section).
I was playing with non-default version of hardware (the bitfile
synthesized for 4-level page memory system) and clearing was helpful,
but then realized support for 4-level page system is untested/broken
in both RocketCore and lowRISC.

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Clear the DDR memory. This should be done by bootloaders,
but they have no such feature yet.

This fixes operation on Rocket Core and lowRISC.

Merge ^/head r294961 through r295350.

MfH @r295202

Expect to see panics in routing code at least now.

MFH

Sponsored by: The FreeBSD Foundation

Welcome the RISC-V 64-bit kernel.

This is the final step required allowing to compile and to run RISC-V
kernel and userland from HEAD.

RISC-V is a completely open ISA that is freely available to ac

Welcome the RISC-V 64-bit kernel.

This is the final step required allowing to compile and to run RISC-V
kernel and userland from HEAD.

RISC-V is a completely open ISA that is freely available to academia
and industry.

Thanks to all the people involved! Special thanks to Andrew Turner,
David Chisnall, Ed Maste, Konstantin Belousov, John Baldwin and
Arun Thomas for their help.
Thanks to Robert Watson for organizing this project.

This project sponsored by UK Higher Education Innovation Fund (HEIF5) and
DARPA CTSRD project at the University of Cambridge Computer Laboratory.

FreeBSD/RISC-V project home: https://wiki.freebsd.org/riscv

Reviewed by: andrew, emaste, kib
Relnotes: Yes
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
Differential Revision: https://reviews.freebsd.org/D4982

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