History log of /freebsd/sys/arm64/intel/stratix10-svc.h (Results 1 – 3 of 3)
Revision (<<< Hide revision tags) (Show revision tags >>>) Date Author Comments
Revision tags: release/14.0.0
# 95ee2897 16-Aug-2023 Warner Losh <imp@FreeBSD.org>

sys: Remove $FreeBSD$: two-line .h pattern

Remove /^\s*\*\n \*\s+\$FreeBSD\$$\n/


Revision tags: release/13.2.0, release/12.4.0, release/13.1.0, release/12.3.0, release/13.0.0, release/12.2.0, release/11.4.0, release/12.1.0
# 61c1328e 13-Sep-2019 Dimitry Andric <dim@FreeBSD.org>

Merge ^/head r352105 through r352307.


# ee41e38d 13-Sep-2019 Ruslan Bukin <br@FreeBSD.org>

Add support for Intel Stratix 10 platform.

Intel Stratix 10 SoC includes a quad-core arm64 cluster and FPGA fabric.

This adds support for reconfiguring FPGA.

Accessing FPGA core of this SoC requir

Add support for Intel Stratix 10 platform.

Intel Stratix 10 SoC includes a quad-core arm64 cluster and FPGA fabric.

This adds support for reconfiguring FPGA.

Accessing FPGA core of this SoC require the level of privilege EL3,
while kernel runs in EL1 (lower) level of privilege.

This provides an Intel service layer interface that uses SMCCC to pass
queries to the secure-monitor (EL3).

Sponsored by: DARPA, AFRL
Differential Revision: https://reviews.freebsd.org/D21454

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