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312a05c3 |
| 22-Mar-2024 |
Brooks Davis <brooks@FreeBSD.org> |
riscv: remove more riscv64sf support
Remove a few more bits of riscv64sf support in libc and libm.
Reduce floating point ABI checks to requiring double hard float.
Reviewed by: imp, jhb
Fixes: 1c
riscv: remove more riscv64sf support
Remove a few more bits of riscv64sf support in libc and libm.
Reduce floating point ABI checks to requiring double hard float.
Reviewed by: imp, jhb
Fixes: 1ca12bd927d7 Remove the riscv64sf architecture.
Differential Revision: https://reviews.freebsd.org/D44334
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Revision tags: release/13.3.0, release/14.0.0 |
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| #
b3e76948 |
| 16-Aug-2023 |
Warner Losh <imp@FreeBSD.org> |
Remove $FreeBSD$: two-line .h pattern
Remove /^\s*\*\n \*\s+\$FreeBSD\$$\n/
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Revision tags: release/13.2.0, release/12.4.0, release/13.1.0, release/12.3.0, release/13.0.0, release/12.2.0, release/11.4.0, release/12.1.0, release/11.3.0, release/12.0.0, release/11.2.0 |
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| #
3b05ffaf |
| 19-Apr-2018 |
Brooks Davis <brooks@FreeBSD.org> |
Replace SOFTFLOAT with __riscv_float_abi_*.
With SOFTFLOAT, libc and libm were built correctly, but any program
including fenv.h itself assumed it was on a hardfloat systen and emitted
inline fpu in
Replace SOFTFLOAT with __riscv_float_abi_*.
With SOFTFLOAT, libc and libm were built correctly, but any program
including fenv.h itself assumed it was on a hardfloat systen and emitted
inline fpu instructions for fedisableexcept() and friends.
Unlike r315424 which did this for MIPS, I've used riscv_float_abi_soft
and riscv_float_abi_double macros as appropriate rather than using
__riscv_float_abi_soft exclusively. This ensures that attempts to use an
unsupported hardfloat ABI will fail.
Reviewed by: br
Sponsored by: DARPA, AFRL
Differential Revision: https://reviews.freebsd.org/D10039
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Revision tags: release/10.4.0, release/11.1.0 |
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| #
67bc8c8b |
| 19-Nov-2016 |
Dimitry Andric <dim@FreeBSD.org> |
Merge ^/head r308491 through r308841.
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| #
7804dd52 |
| 16-Nov-2016 |
Ruslan Bukin <br@FreeBSD.org> |
Add full softfloat and hardfloat support for RISC-V.
Hardfloat is now default (use riscv64sf as TARGET_ARCH
for softfloat).
Sponsored by: DARPA, AFRL
Differential Revision: https://reviews.freebsd.
Add full softfloat and hardfloat support for RISC-V.
Hardfloat is now default (use riscv64sf as TARGET_ARCH
for softfloat).
Sponsored by: DARPA, AFRL
Differential Revision: https://reviews.freebsd.org/D8529
show more ...
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Revision tags: release/11.0.1, release/11.0.0, release/10.3.0 |
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| #
2414e864 |
| 03-Feb-2016 |
Bjoern A. Zeeb <bz@FreeBSD.org> |
MfH @r295202
Expect to see panics in routing code at least now.
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752d0060 |
| 27-Jan-2016 |
Dimitry Andric <dim@FreeBSD.org> |
Merge ^/head r294777 through r294960.
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0e186c0a |
| 27-Jan-2016 |
Glen Barber <gjb@FreeBSD.org> |
MFH
Sponsored by: The FreeBSD Foundation
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| #
4bf1032a |
| 26-Jan-2016 |
Ruslan Bukin <br@FreeBSD.org> |
Add fenv.c for RISC-V. Copied from MIPS.
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