reg.h (4f2c0a4acffbec01079c28f839422e64ddeff004) reg.h (bdb07f35a52f40c461c7da06ddcbaca1950fb9e0)
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright 2014, Michael Ellerman, IBM Corp.
4 */
5
6#ifndef _SELFTESTS_POWERPC_REG_H
7#define _SELFTESTS_POWERPC_REG_H
8

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14 : "=r" (rval)); rval; })
15#define mtspr(rn, v) asm volatile("mtspr " _str(rn) ",%0" : \
16 : "r" ((unsigned long)(v)) \
17 : "memory")
18
19#define mb() asm volatile("sync" : : : "memory");
20#define barrier() asm volatile("" : : : "memory");
21
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright 2014, Michael Ellerman, IBM Corp.
4 */
5
6#ifndef _SELFTESTS_POWERPC_REG_H
7#define _SELFTESTS_POWERPC_REG_H
8

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14 : "=r" (rval)); rval; })
15#define mtspr(rn, v) asm volatile("mtspr " _str(rn) ",%0" : \
16 : "r" ((unsigned long)(v)) \
17 : "memory")
18
19#define mb() asm volatile("sync" : : : "memory");
20#define barrier() asm volatile("" : : : "memory");
21
22#define SPRN_HDEXCR_RO 455 /* Userspace readonly view of SPRN_HDEXCR (471) */
23
22#define SPRN_MMCR2 769
23#define SPRN_MMCRA 770
24#define SPRN_MMCR0 779
25#define MMCR0_PMAO 0x00000080
26#define MMCR0_PMAE 0x04000000
27#define MMCR0_FC 0x80000000
28#define SPRN_EBBHR 804
29#define SPRN_EBBRR 805

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42#define SPRN_PMC4 774
43#define SPRN_PMC5 775
44#define SPRN_PMC6 776
45
46#define SPRN_SIAR 780
47#define SPRN_SDAR 781
48#define SPRN_SIER 768
49
24#define SPRN_MMCR2 769
25#define SPRN_MMCRA 770
26#define SPRN_MMCR0 779
27#define MMCR0_PMAO 0x00000080
28#define MMCR0_PMAE 0x04000000
29#define MMCR0_FC 0x80000000
30#define SPRN_EBBHR 804
31#define SPRN_EBBRR 805

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44#define SPRN_PMC4 774
45#define SPRN_PMC5 775
46#define SPRN_PMC6 776
47
48#define SPRN_SIAR 780
49#define SPRN_SDAR 781
50#define SPRN_SIER 768
51
52#define SPRN_DEXCR_RO 812 /* Userspace readonly view of SPRN_DEXCR (828) */
53
50#define SPRN_TEXASR 0x82 /* Transaction Exception and Status Register */
51#define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */
52#define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */
53#define SPRN_TAR 0x32f /* Target Address Register */
54
55#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF)
56#define SPRN_PVR 0x11F
57

--- 113 unchanged lines hidden --- 		54#define SPRN_TEXASR 0x82 /* Transaction Exception and Status Register */
55#define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */
56#define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */
57#define SPRN_TAR 0x32f /* Target Address Register */
58
59#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF)
60#define SPRN_PVR 0x11F
61

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