misc.c (498495dba268b20e8eadd7fe93c140c68b6cc9d2) misc.c (995d5f64b62f20f05b8e0972f07ec4d6c23333c9)
1// SPDX-License-Identifier: GPL-2.0
2#if defined(__i386__) || defined(__x86_64__)
3
4#include "helpers/helpers.h"
5
6#define MSR_AMD_HWCR 0xc0010015
7
8int cpufreq_has_boost_support(unsigned int cpu, int *support, int *active,

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21 if (cpupower_cpu_info.caps & CPUPOWER_CAP_AMD_CBP) {
22 *support = 1;
23
24 /* AMD Family 0x17 does not utilize PCI D18F4 like prior
25 * families and has no fixed discrete boost states but
26 * has Hardware determined variable increments instead.
27 */
28
1// SPDX-License-Identifier: GPL-2.0
2#if defined(__i386__) || defined(__x86_64__)
3
4#include "helpers/helpers.h"
5
6#define MSR_AMD_HWCR 0xc0010015
7
8int cpufreq_has_boost_support(unsigned int cpu, int *support, int *active,

--- 12 unchanged lines hidden (view full) ---

21 if (cpupower_cpu_info.caps & CPUPOWER_CAP_AMD_CBP) {
22 *support = 1;
23
24 /* AMD Family 0x17 does not utilize PCI D18F4 like prior
25 * families and has no fixed discrete boost states but
26 * has Hardware determined variable increments instead.
27 */
28
29 if (cpu_info.family == 0x17) {
29 if (cpu_info.family == 0x17 || cpu_info.family == 0x18) {
30 if (!read_msr(cpu, MSR_AMD_HWCR, &val)) {
31 if (!(val & CPUPOWER_AMD_CPBDIS))
32 *active = 1;
33 }
34 } else {
35 ret = amd_pci_get_num_boost_states(active, states);
36 if (ret)
37 return ret;
38 }
39 } else if (cpupower_cpu_info.caps & CPUPOWER_CAP_INTEL_IDA)
40 *support = *active = 1;
41 return 0;
42}
43#endif /* #if defined(__i386__) || defined(__x86_64__) */
30 if (!read_msr(cpu, MSR_AMD_HWCR, &val)) {
31 if (!(val & CPUPOWER_AMD_CPBDIS))
32 *active = 1;
33 }
34 } else {
35 ret = amd_pci_get_num_boost_states(active, states);
36 if (ret)
37 return ret;
38 }
39 } else if (cpupower_cpu_info.caps & CPUPOWER_CAP_INTEL_IDA)
40 *support = *active = 1;
41 return 0;
42}
43#endif /* #if defined(__i386__) || defined(__x86_64__) */