instructions.c (539bfea3e09c8e7a773b0fc4f6a4b26d921d63ef) instructions.c (88444952bdfe27fcc91b1c499a0f77675db592a9)
1// SPDX-License-Identifier: GPL-2.0
2#include <linux/compiler.h>
3
4static struct ins_ops *powerpc__associate_instruction_ops(struct arch *arch, const char *name)
5{
6 int i;
7 struct ins_ops *ops;
8

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226 sizeof(arithmetic_two_ops[0]), cmp_offset);
227 if (ret != NULL)
228 return &arithmetic_ops;
229 }
230
231 return NULL;
232}
233
1// SPDX-License-Identifier: GPL-2.0
2#include <linux/compiler.h>
3
4static struct ins_ops *powerpc__associate_instruction_ops(struct arch *arch, const char *name)
5{
6 int i;
7 struct ins_ops *ops;
8

--- 217 unchanged lines hidden (view full) ---

226 sizeof(arithmetic_two_ops[0]), cmp_offset);
227 if (ret != NULL)
228 return &arithmetic_ops;
229 }
230
231 return NULL;
232}
233
234/*
235 * Instruction tracking function to track register state moves.
236 * Example sequence:
237 * ld r10,264(r3)
238 * mr r31,r3
239 * <<after some sequence>
240 * ld r9,312(r31)
241 *
242 * Previous instruction sequence shows that register state of r3
243 * is moved to r31. update_insn_state_powerpc tracks these state
244 * changes
245 */
246#ifdef HAVE_DWARF_SUPPORT
247static void update_insn_state_powerpc(struct type_state *state,
248 struct data_loc_info *dloc, Dwarf_Die * cu_die __maybe_unused,
249 struct disasm_line *dl)
250{
251 struct annotated_insn_loc loc;
252 struct annotated_op_loc *src = &loc.ops[INSN_OP_SOURCE];
253 struct annotated_op_loc *dst = &loc.ops[INSN_OP_TARGET];
254 struct type_state_reg *tsr;
255 u32 insn_offset = dl->al.offset;
256
257 if (annotate_get_insn_location(dloc->arch, dl, &loc) < 0)
258 return;
259
260 /*
261 * Value 444 for bits 21:30 is for "mr"
262 * instruction. "mr" is extended OR. So set the
263 * source and destination reg correctly
264 */
265 if (PPC_21_30(dl->raw.raw_insn) == 444) {
266 int src_reg = src->reg1;
267
268 src->reg1 = dst->reg1;
269 dst->reg1 = src_reg;
270 }
271
272 if (!has_reg_type(state, dst->reg1))
273 return;
274
275 tsr = &state->regs[dst->reg1];
276
277 if (!has_reg_type(state, src->reg1) ||
278 !state->regs[src->reg1].ok) {
279 tsr->ok = false;
280 return;
281 }
282
283 tsr->type = state->regs[src->reg1].type;
284 tsr->kind = state->regs[src->reg1].kind;
285 tsr->ok = true;
286
287 pr_debug_dtp("mov [%x] reg%d -> reg%d",
288 insn_offset, src->reg1, dst->reg1);
289 pr_debug_type_name(&tsr->type, tsr->kind);
290}
291#endif /* HAVE_DWARF_SUPPORT */
292
234static int powerpc__annotate_init(struct arch *arch, char *cpuid __maybe_unused)
235{
236 if (!arch->initialized) {
237 arch->initialized = true;
238 arch->associate_instruction_ops = powerpc__associate_instruction_ops;
239 arch->objdump.comment_char = '#';
240 annotate_opts.show_asm_raw = true;
241 }
242
243 return 0;
244}
293static int powerpc__annotate_init(struct arch *arch, char *cpuid __maybe_unused)
294{
295 if (!arch->initialized) {
296 arch->initialized = true;
297 arch->associate_instruction_ops = powerpc__associate_instruction_ops;
298 arch->objdump.comment_char = '#';
299 annotate_opts.show_asm_raw = true;
300 }
301
302 return 0;
303}