tegra210_sfc.h (03ab8e6297acd1bc0eedaa050e2a1635c576fd11) tegra210_sfc.h (d900d9a435ca95a386f49424f3689cd17ec201da)
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * tegra210_sfc.h - Definitions for Tegra210 SFC driver
4 *
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * tegra210_sfc.h - Definitions for Tegra210 SFC driver
4 *
5 * Copyright (c) 2021 NVIDIA CORPORATION. All rights reserved.
5 * Copyright (c) 2021-2023 NVIDIA CORPORATION. All rights reserved.
6 *
7 */
8
9#ifndef __TEGRA210_SFC_H__
10#define __TEGRA210_SFC_H__
11
12/*
13 * SFC_RX registers are with respect to XBAR.

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42#define TEGRA210_SFC_COEF_RAM 0xbc
43#define TEGRA210_SFC_CFG_RAM_CTRL 0xc0
44#define TEGRA210_SFC_CFG_RAM_DATA 0xc4
45
46/* Fields in TEGRA210_SFC_ENABLE */
47#define TEGRA210_SFC_EN_SHIFT 0
48#define TEGRA210_SFC_EN (1 << TEGRA210_SFC_EN_SHIFT)
49
6 *
7 */
8
9#ifndef __TEGRA210_SFC_H__
10#define __TEGRA210_SFC_H__
11
12/*
13 * SFC_RX registers are with respect to XBAR.

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42#define TEGRA210_SFC_COEF_RAM 0xbc
43#define TEGRA210_SFC_CFG_RAM_CTRL 0xc0
44#define TEGRA210_SFC_CFG_RAM_DATA 0xc4
45
46/* Fields in TEGRA210_SFC_ENABLE */
47#define TEGRA210_SFC_EN_SHIFT 0
48#define TEGRA210_SFC_EN (1 << TEGRA210_SFC_EN_SHIFT)
49
50#define TEGRA210_SFC_NUM_RATES 12
50#define TEGRA210_SFC_NUM_RATES 13
51
52/* Fields in TEGRA210_SFC_COEF_RAM */
53#define TEGRA210_SFC_COEF_RAM_EN BIT(0)
54
55#define TEGRA210_SFC_SOFT_RESET_EN BIT(0)
56
57/* Coefficients */
58#define TEGRA210_SFC_COEF_RAM_DEPTH 64

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52/* Fields in TEGRA210_SFC_COEF_RAM */
53#define TEGRA210_SFC_COEF_RAM_EN BIT(0)
54
55#define TEGRA210_SFC_SOFT_RESET_EN BIT(0)
56
57/* Coefficients */
58#define TEGRA210_SFC_COEF_RAM_DEPTH 64

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