| tegra210_mbdrc.c (14e77332e74603efab8347c89d3cda447c3b97c9) | tegra210_mbdrc.c (f8dc9cd92fe218aa1d8720e1105c542dcd3e58f2) |
|---|---|
| 1// SPDX-License-Identifier: GPL-2.0-only 2// 3// tegra210_mbdrc.c - Tegra210 MBDRC driver 4// 5// Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. 6 7#include <linux/device.h> 8#include <linux/io.h> --- 40 unchanged lines hidden (view full) --- 49 MBDRC_FILTER_REG_DEFAULTS(2), 50}; 51 52/* Default MBDRC parameters */ 53static const struct tegra210_mbdrc_config mbdrc_init_config = { 54 .mode = 0, /* Bypass */ 55 .rms_off = 48, 56 .peak_rms_mode = 1, /* PEAK */ | 1// SPDX-License-Identifier: GPL-2.0-only 2// 3// tegra210_mbdrc.c - Tegra210 MBDRC driver 4// 5// Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. 6 7#include <linux/device.h> 8#include <linux/io.h> --- 40 unchanged lines hidden (view full) --- 49 MBDRC_FILTER_REG_DEFAULTS(2), 50}; 51 52/* Default MBDRC parameters */ 53static const struct tegra210_mbdrc_config mbdrc_init_config = { 54 .mode = 0, /* Bypass */ 55 .rms_off = 48, 56 .peak_rms_mode = 1, /* PEAK */ |
| 57 .fliter_structure = 0, /* All-pass tree */ | 57 .filter_structure = 0, /* All-pass tree */ |
| 58 .shift_ctrl = 30, 59 .frame_size = 32, 60 .channel_mask = 0x3, 61 .fa_factor = 2048, 62 .fr_factor = 14747, 63 64 .band_params[MBDRC_LOW_BAND] = { 65 .band = MBDRC_LOW_BAND, --- 748 unchanged lines hidden (view full) --- 814 conf->rms_off << TEGRA210_MBDRC_CFG_RMS_OFFSET_SHIFT); 815 816 regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG, 817 TEGRA210_MBDRC_CFG_PEAK_RMS_MASK, 818 conf->peak_rms_mode << TEGRA210_MBDRC_CFG_PEAK_RMS_SHIFT); 819 820 regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG, 821 TEGRA210_MBDRC_CFG_FILTER_STRUCTURE_MASK, | 58 .shift_ctrl = 30, 59 .frame_size = 32, 60 .channel_mask = 0x3, 61 .fa_factor = 2048, 62 .fr_factor = 14747, 63 64 .band_params[MBDRC_LOW_BAND] = { 65 .band = MBDRC_LOW_BAND, --- 748 unchanged lines hidden (view full) --- 814 conf->rms_off << TEGRA210_MBDRC_CFG_RMS_OFFSET_SHIFT); 815 816 regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG, 817 TEGRA210_MBDRC_CFG_PEAK_RMS_MASK, 818 conf->peak_rms_mode << TEGRA210_MBDRC_CFG_PEAK_RMS_SHIFT); 819 820 regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG, 821 TEGRA210_MBDRC_CFG_FILTER_STRUCTURE_MASK, |
| 822 conf->fliter_structure << | 822 conf->filter_structure << |
| 823 TEGRA210_MBDRC_CFG_FILTER_STRUCTURE_SHIFT); 824 825 regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG, 826 TEGRA210_MBDRC_CFG_SHIFT_CTRL_MASK, 827 conf->shift_ctrl << TEGRA210_MBDRC_CFG_SHIFT_CTRL_SHIFT); 828 829 regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG, 830 TEGRA210_MBDRC_CFG_FRAME_SIZE_MASK, --- 184 unchanged lines hidden --- | 823 TEGRA210_MBDRC_CFG_FILTER_STRUCTURE_SHIFT); 824 825 regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG, 826 TEGRA210_MBDRC_CFG_SHIFT_CTRL_MASK, 827 conf->shift_ctrl << TEGRA210_MBDRC_CFG_SHIFT_CTRL_SHIFT); 828 829 regmap_update_bits(ope->mbdrc_regmap, TEGRA210_MBDRC_CFG, 830 TEGRA210_MBDRC_CFG_FRAME_SIZE_MASK, --- 184 unchanged lines hidden --- |