tegra20_ac97.c (a1c613ae4c322ddd58d5a8539dbfba2a0380a8c0) tegra20_ac97.c (26e91f61d6b91ccfb0bbb15cbc81845dd1d223af)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * tegra20_ac97.c - Tegra20 AC97 platform driver
4 *
5 * Copyright (c) 2012 Lucas Stach <dev@lynxeye.de>
6 *
7 * Partly based on code copyright/by:
8 *
9 * Copyright (c) 2011,2012 Toradex Inc.
10 */
11
12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <linux/device.h>
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * tegra20_ac97.c - Tegra20 AC97 platform driver
4 *
5 * Copyright (c) 2012 Lucas Stach <dev@lynxeye.de>
6 *
7 * Partly based on code copyright/by:
8 *
9 * Copyright (c) 2011,2012 Toradex Inc.
10 */
11
12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <linux/device.h>
15#include <linux/gpio.h>
15#include <linux/gpio/consumer.h>
16#include <linux/io.h>
17#include <linux/jiffies.h>
18#include <linux/module.h>
19#include <linux/of.h>
16#include <linux/io.h>
17#include <linux/jiffies.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_gpio.h>
21#include <linux/platform_device.h>
22#include <linux/regmap.h>
23#include <linux/reset.h>
24#include <linux/slab.h>
25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>

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34
35static struct tegra20_ac97 *workdata;
36
37static void tegra20_ac97_codec_reset(struct snd_ac97 *ac97)
38{
39 u32 readback;
40 unsigned long timeout;
41
20#include <linux/platform_device.h>
21#include <linux/regmap.h>
22#include <linux/reset.h>
23#include <linux/slab.h>
24#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc.h>

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33
34static struct tegra20_ac97 *workdata;
35
36static void tegra20_ac97_codec_reset(struct snd_ac97 *ac97)
37{
38 u32 readback;
39 unsigned long timeout;
40
42 /* reset line is not driven by DAC pad group, have to toggle GPIO */
43 gpio_set_value(workdata->reset_gpio, 0);
41 /*
42 * The reset line is not driven by DAC pad group, have to toggle GPIO.
43 * The RESET line is active low but this is abstracted by the GPIO
44 * library.
45 */
46 gpiod_set_value(workdata->reset_gpio, 1);
44 udelay(2);
45
47 udelay(2);
48
46 gpio_set_value(workdata->reset_gpio, 1);
49 gpiod_set_value(workdata->reset_gpio, 0);
47 udelay(2);
48
49 timeout = jiffies + msecs_to_jiffies(100);
50
51 do {
52 regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
53 if (readback & TEGRA20_AC97_STATUS1_CODEC1_RDY)
54 break;

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61 u32 readback;
62 unsigned long timeout;
63
64 /*
65 * although sync line is driven by the DAC pad group warm reset using
66 * the controller cmd is not working, have to toggle sync line
67 * manually.
68 */
50 udelay(2);
51
52 timeout = jiffies + msecs_to_jiffies(100);
53
54 do {
55 regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
56 if (readback & TEGRA20_AC97_STATUS1_CODEC1_RDY)
57 break;

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64 u32 readback;
65 unsigned long timeout;
66
67 /*
68 * although sync line is driven by the DAC pad group warm reset using
69 * the controller cmd is not working, have to toggle sync line
70 * manually.
71 */
69 gpio_request(workdata->sync_gpio, "codec-sync");
70
71 gpio_direction_output(workdata->sync_gpio, 1);
72
72 gpiod_direction_output(workdata->sync_gpio, 1);
73 udelay(2);
73 udelay(2);
74 gpio_set_value(workdata->sync_gpio, 0);
74 gpiod_set_value(workdata->sync_gpio, 0);
75 udelay(2);
75 udelay(2);
76 gpio_free(workdata->sync_gpio);
77
78 timeout = jiffies + msecs_to_jiffies(100);
79
80 do {
81 regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
82 if (readback & TEGRA20_AC97_STATUS1_CODEC1_RDY)
83 break;
84 usleep_range(1000, 2000);

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337 ac97->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
338 &tegra20_ac97_regmap_config);
339 if (IS_ERR(ac97->regmap)) {
340 dev_err(&pdev->dev, "regmap init failed\n");
341 ret = PTR_ERR(ac97->regmap);
342 goto err_clk_put;
343 }
344
76
77 timeout = jiffies + msecs_to_jiffies(100);
78
79 do {
80 regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
81 if (readback & TEGRA20_AC97_STATUS1_CODEC1_RDY)
82 break;
83 usleep_range(1000, 2000);

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336 ac97->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
337 &tegra20_ac97_regmap_config);
338 if (IS_ERR(ac97->regmap)) {
339 dev_err(&pdev->dev, "regmap init failed\n");
340 ret = PTR_ERR(ac97->regmap);
341 goto err_clk_put;
342 }
343
345 ac97->reset_gpio = of_get_named_gpio(pdev->dev.of_node,
346 "nvidia,codec-reset-gpio", 0);
347 if (gpio_is_valid(ac97->reset_gpio)) {
348 ret = devm_gpio_request_one(&pdev->dev, ac97->reset_gpio,
349 GPIOF_OUT_INIT_HIGH, "codec-reset");
350 if (ret) {
351 dev_err(&pdev->dev, "could not get codec-reset GPIO\n");
352 goto err_clk_put;
353 }
354 } else {
355 dev_err(&pdev->dev, "no codec-reset GPIO supplied\n");
356 ret = -EINVAL;
344 /* Obtain RESET de-asserted */
345 ac97->reset_gpio = devm_gpiod_get(&pdev->dev,
346 "nvidia,codec-reset",
347 GPIOD_OUT_LOW);
348 if (IS_ERR(ac97->reset_gpio)) {
349 ret = PTR_ERR(ac97->reset_gpio);
350 dev_err(&pdev->dev, "no RESET GPIO supplied: %d\n", ret);
357 goto err_clk_put;
358 }
351 goto err_clk_put;
352 }
353 gpiod_set_consumer_name(ac97->reset_gpio, "codec-reset");
359
354
360 ac97->sync_gpio = of_get_named_gpio(pdev->dev.of_node,
361 "nvidia,codec-sync-gpio", 0);
362 if (!gpio_is_valid(ac97->sync_gpio)) {
363 dev_err(&pdev->dev, "no codec-sync GPIO supplied\n");
364 ret = -EINVAL;
355 ac97->sync_gpio = devm_gpiod_get(&pdev->dev,
356 "nvidia,codec-sync",
357 GPIOD_OUT_LOW);
358 if (IS_ERR(ac97->sync_gpio)) {
359 ret = PTR_ERR(ac97->sync_gpio);
360 dev_err(&pdev->dev, "no codec-sync GPIO supplied: %d\n", ret);
365 goto err_clk_put;
366 }
361 goto err_clk_put;
362 }
363 gpiod_set_consumer_name(ac97->sync_gpio, "codec-sync");
367
368 ac97->capture_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_RX1;
369 ac97->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
370 ac97->capture_dma_data.maxburst = 4;
371
372 ac97->playback_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_TX1;
373 ac97->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
374 ac97->playback_dma_data.maxburst = 4;

--- 88 unchanged lines hidden --- 		364
365 ac97->capture_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_RX1;
366 ac97->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
367 ac97->capture_dma_data.maxburst = 4;
368
369 ac97->playback_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_TX1;
370 ac97->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
371 ac97->playback_dma_data.maxburst = 4;

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