sof-priv.h (1069967afe1e6b728061682ff99ec534a55a5613) sof-priv.h (6e9548cdb30e5d6724236dd7b89a79a270751485)
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2/*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2018 Intel Corporation. All rights reserved.
7 *
8 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>

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64/* convenience constructor for DAI driver streams */
65#define SOF_DAI_STREAM(sname, scmin, scmax, srates, sfmt) \
66 {.stream_name = sname, .channels_min = scmin, .channels_max = scmax, \
67 .rates = srates, .formats = sfmt}
68
69#define SOF_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
70 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_FLOAT)
71
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2/*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2018 Intel Corporation. All rights reserved.
7 *
8 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>

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64/* convenience constructor for DAI driver streams */
65#define SOF_DAI_STREAM(sname, scmin, scmax, srates, sfmt) \
66 {.stream_name = sname, .channels_min = scmin, .channels_max = scmax, \
67 .rates = srates, .formats = sfmt}
68
69#define SOF_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
70 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_FLOAT)
71
72#define ENABLE_DEBUGFS_CACHEBUF \
73 (IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_ENABLE_DEBUGFS_CACHE) || \
74 IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_IPC_FLOOD_TEST))
75
76/* So far the primary core on all DSPs has ID 0 */
77#define SOF_DSP_PRIMARY_CORE 0
78
79/* max number of DSP cores */
80#define SOF_MAX_DSP_NUM_CORES 8
81
82struct sof_dsp_power_state {
83 u32 state;

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321 size_t buf_data_size; /* length of buffered data for file read operation */
322 enum sof_dfsentry_type type;
323 /*
324 * access_type specifies if the
325 * memory -> DSP resource (memory, register etc) is always accessible
326 * or if it is accessible only when the DSP is in D0.
327 */
328 enum sof_debugfs_access_type access_type;
72/* So far the primary core on all DSPs has ID 0 */
73#define SOF_DSP_PRIMARY_CORE 0
74
75/* max number of DSP cores */
76#define SOF_MAX_DSP_NUM_CORES 8
77
78struct sof_dsp_power_state {
79 u32 state;

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317 size_t buf_data_size; /* length of buffered data for file read operation */
318 enum sof_dfsentry_type type;
319 /*
320 * access_type specifies if the
321 * memory -> DSP resource (memory, register etc) is always accessible
322 * or if it is accessible only when the DSP is in D0.
323 */
324 enum sof_debugfs_access_type access_type;
329#if ENABLE_DEBUGFS_CACHEBUF
325#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_ENABLE_DEBUGFS_CACHE)
330 char *cache_buf; /* buffer to cache the contents of debugfs memory */
331#endif
332#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_IPC_MSG_INJECTOR)
333 void *msg_inject_tx;
334 void *msg_inject_rx;
335#endif
336 struct snd_sof_dev *sdev;
337 struct list_head list; /* list in sdev dfsentry list */

--- 361 unchanged lines hidden --- 		326 char *cache_buf; /* buffer to cache the contents of debugfs memory */
327#endif
328#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_IPC_MSG_INJECTOR)
329 void *msg_inject_tx;
330 void *msg_inject_rx;
331#endif
332 struct snd_sof_dev *sdev;
333 struct list_head list; /* list in sdev dfsentry list */

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