| acp.h (4da6b033f5454ccbac2d5795d7edfb3f2a777104) | acp.h (41cb85bc4b526bb228579c04857bc58213e5f9b5) |
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| 1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2/* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved. 7 * 8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> --- 17 unchanged lines hidden (view full) --- 26#define ACP_PGFSM_STATUS_MASK 0x03 27#define ACP_POWERED_ON 0x00 28#define ACP_ASSERT_RESET 0x01 29#define ACP_RELEASE_RESET 0x00 30#define ACP_SOFT_RESET_DONE_MASK 0x00010001 31 32#define ACP_DSP_INTR_EN_MASK 0x00000001 33#define ACP3X_SRAM_PTE_OFFSET 0x02050000 | 1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2/* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved. 7 * 8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> --- 17 unchanged lines hidden (view full) --- 26#define ACP_PGFSM_STATUS_MASK 0x03 27#define ACP_POWERED_ON 0x00 28#define ACP_ASSERT_RESET 0x01 29#define ACP_RELEASE_RESET 0x00 30#define ACP_SOFT_RESET_DONE_MASK 0x00010001 31 32#define ACP_DSP_INTR_EN_MASK 0x00000001 33#define ACP3X_SRAM_PTE_OFFSET 0x02050000 |
| 34#define ACP6X_SRAM_PTE_OFFSET 0x03800000 |
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| 34#define PAGE_SIZE_4K_ENABLE 0x2 35#define ACP_PAGE_SIZE 0x1000 36#define ACP_DMA_CH_RUN 0x02 37#define ACP_MAX_DESC_CNT 0x02 38#define DSP_FW_RUN_ENABLE 0x01 39#define ACP_SHA_RUN 0x01 40#define ACP_SHA_RESET 0x02 41#define ACP_DMA_CH_RST 0x01 --- 7 unchanged lines hidden (view full) --- 49#define ACP_SYSTEM_MEMORY_WINDOW 0x4000000 50#define ACP_IRAM_BASE_ADDRESS 0x000000 51#define ACP_DATA_RAM_BASE_ADDRESS 0x01000000 52#define ACP_DRAM_PAGE_COUNT 128 53 54#define ACP_DSP_TO_HOST_IRQ 0x04 55 56#define HOST_BRIDGE_CZN 0x1630 | 35#define PAGE_SIZE_4K_ENABLE 0x2 36#define ACP_PAGE_SIZE 0x1000 37#define ACP_DMA_CH_RUN 0x02 38#define ACP_MAX_DESC_CNT 0x02 39#define DSP_FW_RUN_ENABLE 0x01 40#define ACP_SHA_RUN 0x01 41#define ACP_SHA_RESET 0x02 42#define ACP_DMA_CH_RST 0x01 --- 7 unchanged lines hidden (view full) --- 50#define ACP_SYSTEM_MEMORY_WINDOW 0x4000000 51#define ACP_IRAM_BASE_ADDRESS 0x000000 52#define ACP_DATA_RAM_BASE_ADDRESS 0x01000000 53#define ACP_DRAM_PAGE_COUNT 128 54 55#define ACP_DSP_TO_HOST_IRQ 0x04 56 57#define HOST_BRIDGE_CZN 0x1630 |
| 58#define HOST_BRIDGE_RMB 0x14B5 |
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| 57#define ACP_SHA_STAT 0x8000 58#define ACP_PSP_TIMEOUT_COUNTER 5 59#define ACP_EXT_INTR_ERROR_STAT 0x20000000 60#define MP0_C2PMSG_114_REG 0x3810AC8 61#define MP0_C2PMSG_73_REG 0x3810A24 62#define MBOX_ACP_SHA_DMA_COMMAND 0x70000 63#define MBOX_DELAY 1000 64#define MBOX_READY_MASK 0x80000000 --- 80 unchanged lines hidden (view full) --- 145 unsigned int i2s_mode; 146 u32 pgfsm_base; 147 u32 ext_intr_stat; 148 u32 dsp_intr_base; 149 u32 sram_pte_offset; 150 u32 i2s_pin_config_offset; 151 u32 hw_semaphore_offset; 152 u32 acp_clkmux_sel; | 59#define ACP_SHA_STAT 0x8000 60#define ACP_PSP_TIMEOUT_COUNTER 5 61#define ACP_EXT_INTR_ERROR_STAT 0x20000000 62#define MP0_C2PMSG_114_REG 0x3810AC8 63#define MP0_C2PMSG_73_REG 0x3810A24 64#define MBOX_ACP_SHA_DMA_COMMAND 0x70000 65#define MBOX_DELAY 1000 66#define MBOX_READY_MASK 0x80000000 --- 80 unchanged lines hidden (view full) --- 147 unsigned int i2s_mode; 148 u32 pgfsm_base; 149 u32 ext_intr_stat; 150 u32 dsp_intr_base; 151 u32 sram_pte_offset; 152 u32 i2s_pin_config_offset; 153 u32 hw_semaphore_offset; 154 u32 acp_clkmux_sel; |
| 155 u32 fusion_dsp_offset; |
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| 153}; 154 155/* Common device data struct for ACP devices */ 156struct acp_dev_data { 157 struct snd_sof_dev *dev; 158 unsigned int fw_bin_size; 159 unsigned int fw_data_bin_size; 160 u32 fw_bin_page_count; --- 57 unchanged lines hidden (view full) --- 218int acp_pcm_hw_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream, 219 struct snd_pcm_hw_params *params, 220 struct snd_sof_platform_stream_params *platform_params); 221 222extern struct snd_sof_dsp_ops sof_acp_common_ops; 223 224extern struct snd_sof_dsp_ops sof_renoir_ops; 225int sof_renoir_ops_init(struct snd_sof_dev *sdev); | 156}; 157 158/* Common device data struct for ACP devices */ 159struct acp_dev_data { 160 struct snd_sof_dev *dev; 161 unsigned int fw_bin_size; 162 unsigned int fw_data_bin_size; 163 u32 fw_bin_page_count; --- 57 unchanged lines hidden (view full) --- 221int acp_pcm_hw_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream, 222 struct snd_pcm_hw_params *params, 223 struct snd_sof_platform_stream_params *platform_params); 224 225extern struct snd_sof_dsp_ops sof_acp_common_ops; 226 227extern struct snd_sof_dsp_ops sof_renoir_ops; 228int sof_renoir_ops_init(struct snd_sof_dev *sdev); |
| 229extern struct snd_sof_dsp_ops sof_rembrandt_ops; 230int sof_rembrandt_ops_init(struct snd_sof_dev *sdev); |
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| 226 227int acp_dai_probe(struct snd_soc_dai *dai); 228struct snd_soc_acpi_mach *amd_sof_machine_select(struct snd_sof_dev *sdev); 229/* Machine configuration */ 230int snd_amd_acp_find_config(struct pci_dev *pci); 231 232/* Trace */ 233int acp_sof_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, --- 14 unchanged lines hidden --- | 231 232int acp_dai_probe(struct snd_soc_dai *dai); 233struct snd_soc_acpi_mach *amd_sof_machine_select(struct snd_sof_dev *sdev); 234/* Machine configuration */ 235int snd_amd_acp_find_config(struct pci_dev *pci); 236 237/* Trace */ 238int acp_sof_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, --- 14 unchanged lines hidden --- |