acp.h (03ab8e6297acd1bc0eedaa050e2a1635c576fd11) acp.h (b585692fc937dc8f9d494078b5ffe2aafe31ec18)
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2/*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
7 *
8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>

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52#define ACP_DRAM_PAGE_COUNT 128
53
54#define ACP_DSP_TO_HOST_IRQ 0x04
55
56#define HOST_BRIDGE_CZN 0x1630
57#define ACP_SHA_STAT 0x8000
58#define ACP_PSP_TIMEOUT_COUNTER 5
59#define ACP_EXT_INTR_ERROR_STAT 0x20000000
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2/*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
7 *
8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>

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52#define ACP_DRAM_PAGE_COUNT 128
53
54#define ACP_DSP_TO_HOST_IRQ 0x04
55
56#define HOST_BRIDGE_CZN 0x1630
57#define ACP_SHA_STAT 0x8000
58#define ACP_PSP_TIMEOUT_COUNTER 5
59#define ACP_EXT_INTR_ERROR_STAT 0x20000000
60#define MP0_C2PMSG_26_REG 0x03810570
61#define MBOX_ACP_SHA_DMA_COMMAND 0x330000
60#define MP0_C2PMSG_114_REG 0x3810AC8
61#define MP0_C2PMSG_73_REG 0x3810A24
62#define MBOX_ACP_SHA_DMA_COMMAND 0x70000
63#define MBOX_DELAY 1000
62#define MBOX_READY_MASK 0x80000000
63#define MBOX_STATUS_MASK 0xFFFF
64
65struct acp_atu_grp_pte {
66 u32 low;
67 u32 high;
68};
69

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199 * DSP PCM Operations.
200 */
201int acp_pcm_open(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream);
202int acp_pcm_close(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream);
203int acp_pcm_hw_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream,
204 struct snd_pcm_hw_params *params,
205 struct snd_sof_platform_stream_params *platform_params);
206
64#define MBOX_READY_MASK 0x80000000
65#define MBOX_STATUS_MASK 0xFFFF
66
67struct acp_atu_grp_pte {
68 u32 low;
69 u32 high;
70};
71

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201 * DSP PCM Operations.
202 */
203int acp_pcm_open(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream);
204int acp_pcm_close(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream);
205int acp_pcm_hw_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream,
206 struct snd_pcm_hw_params *params,
207 struct snd_sof_platform_stream_params *platform_params);
208
207extern const struct snd_sof_dsp_ops sof_renoir_ops;
209extern struct snd_sof_dsp_ops sof_renoir_ops;
208
209/* Machine configuration */
210int snd_amd_acp_find_config(struct pci_dev *pci);
211
212/* Trace */
210
211/* Machine configuration */
212int snd_amd_acp_find_config(struct pci_dev *pci);
213
214/* Trace */
213int acp_sof_trace_init(struct snd_sof_dev *sdev,
215int acp_sof_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
214 struct sof_ipc_dma_trace_params_ext *dtrace_params);
215int acp_sof_trace_release(struct snd_sof_dev *sdev);
216
216 struct sof_ipc_dma_trace_params_ext *dtrace_params);
217int acp_sof_trace_release(struct snd_sof_dev *sdev);
218
219/* PM Callbacks */
220int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state);
221int amd_sof_acp_resume(struct snd_sof_dev *sdev);
222
217struct sof_amd_acp_desc {
218 unsigned int host_bridge_id;
219};
220
221static inline const struct sof_amd_acp_desc *get_chip_info(struct snd_sof_pdata *pdata)
222{
223 const struct sof_dev_desc *desc = pdata->desc;
224
225 return desc->chip_info;
226}
227#endif
223struct sof_amd_acp_desc {
224 unsigned int host_bridge_id;
225};
226
227static inline const struct sof_amd_acp_desc *get_chip_info(struct snd_sof_pdata *pdata)
228{
229 const struct sof_dev_desc *desc = pdata->desc;
230
231 return desc->chip_info;
232}
233#endif